METHOD OF MANUFACTURING DEVICE

• US 20130023095A1
• Filed: 07/19/2012
• Published: 01/24/2013
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: NOJIMA, Kazuhiro
• Granted Patent: US 8,883,593 B2
• Time in Patent Office: Days
• US Class Current: 438/268
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A semiconductor pillar which has a first conductive type and protrudes from a semiconductor substrate, is formed. A bottom diffusion layer having a second conductive type is formed in the semiconductor substrate around a bottom of the semiconductor pillar. A gate insulator film which covers a side surface of the semiconductor pillar, is formed. A gate electrode which covers the gate insulator film, is formed. A top diffusion layer having the second conductive type is formed at a top portion of the semiconductor pillar. The top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

Claims

1. A method of manufacturing a device, comprising:

forming a semiconductor pillar having a first conductive type protruding from a semiconductor substrate;

forming a bottom diffusion layer having a second conductive type in the semiconductor substrate around a bottom of the semiconductor pillar;

forming a gate insulator film covering a side surface of the semiconductor pillar;

forming a gate electrode covering the gate insulator film; and

forming a top diffusion layer having the second conductive type at a top portion of the semiconductor pillar, the top diffusion layer including a semiconductor body is formed by an epitaxial growth which contains an impurity.

2. The method of manufacturing the device according to claim 1, further comprising after the forming the gate electrode and before the forming the top diffusion layer;

forming a lightly doped drain layer having the second conductive type at the top portion of the semiconductor pillar by implanting an impurity.

3. The method of manufacturing the device according to claim 1, wherein the first conductive type is p-type and the second conductive type is n-type.

4. The method of manufacturing the device according to claim 3, wherein the epitaxial growth uses source gases including a doping gas which contains at least one of phosphorus and arsenic.

5. The method of manufacturing the device according to claim 1, wherein the first conductive type is n-type and the second conductive type is p-type.

6. The method of manufacturing the device according to claim 5, wherein the epitaxial growth uses source gases including a doping gas which contains boron.

7. The method of manufacturing the device according to claim 1, wherein the forming the semiconductor pillar is to form a plurality of the semiconductor pillars having same diameter each other.

8. The method of manufacturing the device according to claim 1, wherein the forming the semiconductor pillar is to form a plurality of the semiconductor pillars having different diameters respectively.

9. The method of manufacturing the device according to claim 8, wherein the forming the top diffusion layer is to form most top diffusion layers having same impurity concentration of each other.

10. The method of manufacturing the device according to claim 8, wherein the forming the top diffusion layer is to form the plurality of the semiconductor pillars having different impurity concentrations each associated with different diameters.

11. The method of manufacturing the device according to claim 10,

wherein the forming the semiconductor pillar is to form a first semiconductor pillar and a plurality of second semiconductor pillars, the second semiconductor pillars having bigger diameter than the first semiconductor pillar;

wherein the forming the top diffusion layer further comprises;

forming a mask layer which covers the first semiconductor pillar;

forming a fourth diffusion layer of a first impurity concentration over a top portion of the second semiconductor pillar by the epitaxial growth;

forming an insulating layer which covers the top portion of the fourth diffusion layer;

removing the mask layer and exposing a top portion of the first semiconductor pillar; and

forming a third diffusion layer of a second impurity concentration over the top portion of the first semiconductor pillar by the epitaxial growth.

12. The method of manufacturing the device according to claim 1,

wherein the forming the semiconductor pillar is to form a first semiconductor pillar and a second semiconductor pillar, the first semiconductor pillar including an impurity of providing n-type semiconductor being disposed in n-well region and the second semiconductor pillar including a impurity of providing p-type semiconductor being disposed in p-well region;

wherein the forming the bottom diffusion layer further comprises;

forming a first mask layer which covers the n-well region;

forming, with using the first mask layer as a mask, a second diffusion layer by implanting an impurity of providing n-type semiconductor in the semiconductor substrate around a bottom of the second semiconductor pillar which is in the p-well region;

removing the first mask layer;

forming a second mask layer which covers the p-well region;

forming, with using the second mask layer as a mask, a first diffusion layer by implanting an impurity of providing p-type semiconductor in the semiconductor substrate around a bottom of the first semiconductor pillar which is in the n-well region; and

removing the second mask layer;

wherein the forming the top diffusion layer further comprises;

forming a third mask layer which covers the n-well region;

forming a fourth diffusion layer by an epitaxial growth of a semiconductor which includes an impurity of providing n-type semiconductor at a top portion of the second semiconductor pillar;

forming an insulating layer over the fourth diffusion layer;

removing the third mask layer; and

forming a third diffusion layer by an epitaxial growth of a semiconductor which includes an impurity of providing p-type semiconductor at a top portion of the first semiconductor pillar.

13. The method of manufacturing the device according to claim 12,

further comprising after the forming the third mask layer and before the forming the fourth diffusion layer, forming a lightly doped drain layer by implanting an impurity of forming the n-type semiconductor at the top portion of the second semiconductor pillar;

further comprising after the removing the third mask layer and before the forming the third diffusion layer, forming a lightly doped drain layer by implanting an impurity of forming the p-type semiconductor at the top portion of the first semiconductor pillar.

14. The method of manufacturing the device according to claim 12, wherein the forming the insulating layer is to form a silicon oxide on the fourth diffusion layer using any one of three methods as follows:

(1) oxidation by mixing oxygen in source gases at the last step of the epitaxial growth,

(2) thermal oxidation using oxygen ambient,

(3) chemical oxidation using an oxidizer.

15. The method of manufacturing the device according to claim 14, wherein the oxidizer is nitric acid.

16. The method of manufacturing the device according to claim 12, wherein each of the third and the fourth diffusion layers has impurity concentration ranging from 1.0×

10¹⁹ cm<sup>−

3</sup> to 1.0×

10²⁰ cm<sup>−

3</sup>, respectively.

17. The method of manufacturing the device according to claim 1, further comprising after the forming the top diffusion layer:

forming a storage element to connect the top diffusion layer electrically, the storage element having an upper electrode and a lower electrode; and

forming a bit line which connects to the one of the upper electrode and the lower electrode electrically.

18. A method of manufacturing a device, comprising:

forming a semiconductor pillar protruding from a semiconductor substrate having a first conductive type;

forming a bottom diffusion layer having a second conductive type in the semiconductor substrate around a bottom of the semiconductor pillar;

forming a gate insulator film covering a side surface of the semiconductor pillar;

forming a gate electrode covering the gate insulator film; and

forming a top diffusion layer having the second conductive type at a top portion of the semiconductor pillar.

19. The method of manufacturing the device according to claim 18, wherein the top diffusion layer includes a polycrystalline semiconductor containing an impurity formed by a low pressure chemical vapor deposition.

20. The method of manufacturing the device according to claim 19, further comprising after the forming the gate electrode and before the forming the top diffusion layer;

forming a lightly doped drain layer having the second conductive type at the top portion of the semiconductor pillar by implanting an impurity.