DEVICE PROGRAMMING SYSTEM WITH DATA BROADCAST AND METHOD OF OPERATION THEREOF

• US 20130024603A1
• Filed: 07/20/2011
• Published: 01/24/2013
• Est. Priority Date: 07/20/2011
• Status: Active Grant

• Current Assignee: Data I/O Corporation
• Original Assignee: Data I/O Corporation
• Inventors: Caley, Andrew B., Steffey, Derek P.
• Granted Patent: US 9,720,681 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 8/654 using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories

Abstract

A method of operation of a device programming system includes: providing a target programmer, having a programming bus; coupling an electronic device, having a non-volatile memory, to the target programmer by the programming bus; and programming a data image into the non-volatile memory by the target programmer includes: subscribing to a broadcast message, receiving a logical block, of the data image, by the broadcast message for programming the non-volatile memory, and sending an unsubscribe message after receiving the logical blocks of the data image from the broadcast message.

Claims

1. A method of operation of a device programming system comprising:

providing a target programmer, having a programming bus;

coupling an electronic device, having a non-volatile memory, to the target programmer by the programming bus; and

programming a data image into the non-volatile memory by the target programmer including;

subscribing to a broadcast message,

receiving a logical block, of the data image, by the broadcast message for programming the non-volatile memory, and

sending an unsubscribe message after receiving the logical blocks of the data image from the broadcast message.

2. The method as claimed in claim 1 wherein providing the target programmer includes providing a first target programmer and a second target programmer.

3. The method as claimed in claim 1 further comprising providing a data buffer in the target programmer for receiving the logical block from the broadcast message.

4. The method as claimed in claim 1 further comprising initializing a logical block address map in the target programmer.

5. The method as claimed in claim 1 wherein receiving the logical block includes receiving a mid-stream logical block.

6. A method of operation of a device programming system comprising:

providing a target programmer, having a programming bus;

coupling a data broadcast bus to the target programmer;

coupling an electronic device, having a non-volatile memory, to the target programmer by the programming bus; and

programming a data image into the non-volatile memory by the target programmer including;

subscribing to a broadcast message,

receiving a logical block, of the data image, by the broadcast message for programming the non-volatile memory, and

sending an unsubscribe message after receiving the logical blocks of the data image from the broadcast message.

7. The method as claimed in claim 6 wherein providing the target programmer includes providing a first target programmer, a second target programmer, a third target programmer, through an Nth target programmer.

8. The method as claimed in claim 6 further comprising providing a data buffer in the target programmer for receiving the logical block from the broadcast message including receiving, by a first target programmer, a second target programmer, a third target programmer, through an Nth target programmer, the broadcast message having the logical block.

9. The method as claimed in claim 6 further comprising initializing a logical block address map in the target programmer;

and

wherein;

initializing the logical block address map includes initializing a first target programmer, a second target programmer, a third target programmer, through an Nth target programmer with the logical block address map.

10. The method as claimed in claim 6 wherein receiving the logical block includes receiving a mid-stream logical block, a first of file logical block, and an end of file logical block in an out-of-order transfer.

11. A device programming system comprising:

a target programmer, having a programming bus;

an electronic device, having a non-volatile memory, coupled to the target programmer by the programming bus; and

a data image programmed into the non-volatile memory by the target programmer including;

a host server subscribed for sending a broadcast message, and

a data buffer in the target programmer for receiving the broadcast message.

12. The system as claimed in claim 11 further comprising a first target programmer and a second target programmer each coupled to units of the electronic device.

13. The system as claimed in claim 11 wherein the data buffer in the target programmer for receiving the logical block from the broadcast message includes a first target programmer and a second target programmer each having the data buffer.

14. The system as claimed in claim 11 further comprising a logical block address map in the data buffer of the target programmer.

15. The system as claimed in claim 11 further comprising a data broadcast bus between the host server and the target programmer.

16. The system as claimed in claim 11 wherein the target programmer includes a first target programmer and a second target programmer coupled to the host server.

17. The system as claimed in claim 16 wherein the target programmer includes a third target programmer through an Nth target programmer.

18. The system as claimed in claim 16 further comprising a data broadcast bus from the host server to the first target programmer and the second target programmer.

19. The system as claimed in claim 16 further comprising a logical block address map in the data buffer of the first target programmer and the second target programmer.

20. The system as claimed in claim 16 further comprising a data buffer in the first target programmer and the second target programmer for verifying the content of the non-volatile memory.