STRUCTURED MEMORY COPROCESSOR

• US 20130024645A1
• Filed: 05/20/2010
• Published: 01/24/2013
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Hicamp Systems Incorporated
• Inventors: Cheriton, David R., Solomatnikov, Alexandre Y.
• Granted Patent: US 8,407,428 B2
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 12/10 Address translation

Abstract

Intercepting a requested memory operation corresponding to a conventional memory is disclosed. The requested memory operation is translated to be applied to a structured memory.

Claims

1. A computer system comprising:

an interconnect;

a conventional memory;

a processor coupled to the interconnect, wherein the processor requests a memory operation corresponding to the conventional memory over the interconnect for an executing process;

a structured memory;

and

a coprocessor coupled to the interconnect, wherein;

the coprocessor is associated with the structured memory;

the coprocessor is configured to;

intercept the requested memory operation;

determine an execution context for the executing process;

provide direct memory access (“

DMA”

) to the structured memory with isolation between the executing process and any other process, at least in part by exporting the executing context as a physical page in structured memory; and

translate the requested memory operation corresponding to the conventional memory to be applied to the structured memory.

2. A computer system as recited in claim 1, further comprising a conventional memory coupled to the interconnect.

3. A computer system as recited in claim 1, wherein the requested memory operation is addressed within a mapped region.

4. A computer system as recited in claim 1, wherein the requested memory operation is addressed within a physical address region associated with the coprocessor.

5. A computer system as recited in claim 1, wherein the requested memory operation is addressed within a physical address region associated with the coprocessor, specified by a developer.

6. A computer system as recited in claim 1, wherein the requested memory operation is addressed within a physical address region associated with the coprocessor, specified by an operating system.

7. A computer system as recited in claim 1, wherein the requested memory operation is addressed within a physical address region associated with the coprocessor, transparent to a developer.

8. A computer system as recited in claim 1, wherein the interconnect is a coherent memory bus.

9. A computer system as recited in claim 1, wherein the requested memory operation comprises an indirect read or an indirect write.

10. A computer system as recited in claim 1, wherein the requested memory operation comprises an atomic update operation.

11. A computer system as recited in claim 1, wherein the requested memory operation represents a key-value pair lookup.

12. A computer system as recited in claim 1, wherein the structured memory is hierarchical.

13. A computer system as recited in claim 1, wherein the structured memory is immutable.

14. A computer system as recited in claim 1, wherein the structured memory is deduplicated.

15. A computer system as recited in claim 1, wherein the structured memory is content addressable.

16. A computer system as recited in claim 1, wherein the structured memory provides snapshot checkpointing.

17. A computer system as recited in claim 1, wherein the structured memory represents a database.

18. A computer system as recited in claim 1, wherein the structured memory represents a snapshot of state for lock-free execution.

19. A computer system as recited in claim 1, wherein the structured memory represents an inverted index.

20. A computer system as recited in claim 1, wherein the structured memory represents a sparse matrix.

21. A computer system as recited in claim 1, wherein the coprocessor and structured memory represent a memcached server to the processor.

22. A computer system as recited in claim 1, wherein the coprocessor and structured memory represent a search engine to the processor.

23. A computer system as recited in claim 1, wherein the coprocessor is further configured to return to the processor a result of the translated memory operation applied to the structured memory.

24. A computer system as recited in claim 1, wherein the memory operation is a writing operation and the coprocessor applies the writing operation to a transient line before committing the writing operation to the structured memory.

25. A computer system as recited in claim 1, wherein the coprocessor includes a cache memory.

26. A method comprising:

intercepting a requested memory operation corresponding to a conventional memory for an executing process;

determining an execution context for the executing process;

providing for the executing process direct memory access (“

DMA”

) to the structured memory with isolation between the executing process and any other process, at least in part by exporting the executing context as a physical page in structured memory; and

translating the requested memory operation corresponding to the conventional memory to be applied to a structured memory.

27. A method as recited in claim 26, wherein the requested memory operation is addressed within a mapped region.

28. A method as recited in claim 26, wherein the requested memory operation comprises an atomic update operation.

29. A method as recited in claim 26, wherein the requested memory operation represents a key-value pair lookup.

30. A method as recited in claim 26, wherein the structured memory is hierarchical.

31. A method as recited in claim 26, wherein the structured memory is immutable.

32. A method as recited in claim 26, wherein the structured memory is deduplicated.

33. A method as recited in claim 26, wherein the structured memory is content addressable.

34. A method as recited in claim 26, wherein the structured memory provides snapshot checkpointing.

35. A method as recited in claim 26, wherein the structured memory represents a database.

36. A method as recited in claim 26, wherein the structured memory represents a snapshot of state for lock-free execution.

37. A method as recited in claim 26, wherein the structured memory represents an inverted index.

38. A method as recited in claim 26, wherein the structured memory represents a sparse matrix.

39. A method as recited in claim 26, further comprising returning a result of the translated memory operation applied to the structured memory.

40. A method as recited in claim 26, wherein the requested memory operation is a writing operation and further comprising applying the writing operation to a transient line before committing the writing operation to the structured memory.