Control flow integrity
First Claim
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1. A processor comprising:
- logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception.
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Abstract
In at least some embodiments, a processor in accordance with the present disclosure is operable to enforce control flow integrity. For examiner, a processor may comprise logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception.
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Citations
46 Claims
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1. A processor comprising:
logic operable to execute a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A processor comprising:
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an instruction decoder operable to decode a control flow integrity instruction; and an execution logic coupled to the instruction decoder and operable to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. - View Dependent Claims (15, 16, 17, 18, 19)
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20-33. -33. (canceled)
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34. A data processing apparatus comprising:
a data security logic operable to use a control flow integrity instruction specified to verify changes in control flow and respond to verification failure by at least one of a trap or an exception. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45)
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46-70. -70. (canceled)
Specification