SOLID-STATE MEMORY-BASED STORAGE METHOD AND DEVICE WITH LOW ERROR RATE

• US 20130024735A1
• Filed: 07/19/2011
• Published: 01/24/2013
• Est. Priority Date: 07/19/2011
• Status: Abandoned Application

• Current Assignee: OCZ Storage Solutions Incorporated (Toshiba Corporation)
• Original Assignee: OCZ Technology Group, Inc. (Toshiba Corporation)
• Inventors: Schuette, Franz Michael, Chung, Hyun Mo
• Application Number:
  US13/185,689
• Publication Number:
  US 20130024735A1
• Time in Patent Office: Days
• US Class Current: 714/704
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 11/1415 at system level
• CPC Class Codes: G06F 11/2084 on the same storage unit

Abstract

Non-volatile solid-state memory-based storage devices and methods of operating the storage devices to have low initial error rates. The storage devices and methods use bit error rate comparison of duplicate writes to one or more non-volatile memory devices. The data set with a lower bit error rate as determined during verification is maintained, whereas data sets with higher bit error rates are discarded. A threshold of bit error rates can be used to trigger the duplication of data for bit error comparison.

Claims

1. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:

receiving data from a host system;

writing a first copy of the data to a first address in the memory devices of the storage device;

checking a bit error rate of the first copy of the data written to the memory devices using an error checking and correction (ECC) implementation; and

writing a second copy of the data to a second address in the memory devices if the bit error rate of the first copy exceeds a threshold, the threshold being lower than or equal to an uncorrectable bit error rate threshold of the data associated with the ECC implementation.

2. The method of claim 1, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.

3. The method of claim 1 wherein, if the bit error rate of the first copy and a bit error rate of the second copy are above the threshold, the data are written to a third location in the memory devices.

4. The method of claims 1, wherein the threshold is one-half of a maximum correctable bit error rate of the data using the ECC implementation.

5. The method of claim 1, wherein the threshold is biased by patterns of errors in the first and second copies of the data.

6. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:

receiving data from a host system;

encoding the data with the storage device for error checking and correction using an error checking and correction (ECC) implementation;

writing a first copy of the data to a first address in the memory devices;

checking a bit error rate of the first copy of the data written to the memory devices; and

writing a second copy of the data to a second address in the memory devices if the bit error rate of the first copy exceeds a threshold, the threshold not exceeding an uncorrectable bit error rate threshold of the data associated with the ECC implementation.

7. The method of claim 6, wherein the non-volatile solid-state memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.

8. The method of claim 6 wherein, if the bit error rate of the first copy and a bit error rate of the second copy are above the threshold, the data are written to a third location in the memory devices.

9. The method of claims 6, wherein the threshold of the bit error rate is one-half of a maximum correctable bit error rate of the data using the ECC implementation.

10. The method of claim 8, wherein the threshold is biased by patterns of errors in the first and second copies of the data.

11. A method for increasing the data integrity of a non-volatile solid-state memory-based storage device comprising one or more non-volatile memory devices, the method comprising:

receiving data from a host system;

encoding the data with the storage device for error checking and correction using an error checking and correction (ECC) implementation;

writing a first copy and a second copy of the data to a first address and a second address, respectively, in the memory devices;

checking the bit error rates of the first and second copies of the data written to the memory devices; and

discarding either of the first and second copies having a higher bit error rate.

12. The method of claim 11, further comprising:

logging of bit error rates of blocks of the memory devices;

calculating an average bit error rate for each block; and

if the average bit error rate of a block exceeds a threshold, erasing the block and suspending the block from use by the storage device until the average wear count of all blocks has increased an incremental number of cycles.

13. The method of claim 12 where the incremental number of cycles of the average wear count is a percentage of program/erase cycles logged for the block.

14. The method of claim 11, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.

15. A mass storage device comprising a host system interface and a printed circuit board having a controller and one or more solid-state non-volatile memory devices mounted thereon, the memory devices being addressable individually over discrete channels of the controller, the controller comprising:

an error checking and correction (ECC) engine operable to encode data written from a host system to the storage device according to an ECC algorithm and to determine bit error rates of data written to the memory devices;

means for writing a set of the data to a first address of the memory devices and, if the bit error rate of the set of data is within a range acceptable for error correction but exceeds a threshold, writing a copy of the set of the data to a second address of the memory devices; and

means for comparing the bit error rate of the copy of the set of the data written to the second address to the bit error rate of the set of the data written to the first address and discarding the set of the data or the copy thereof having a higher bit error rate.

16. The mass storage device of claim 15, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.

17. A solid-state mass storage device comprising a controller, a cache memory, and one or more non-volatile memory devices, the memory devices each being connected to an independent channel of the controller, the controller comprising:

an error checking and correction (ECC) engine for ECC-encoding data written from a host system to the storage device before writing the ECC-encoded data to one of the memory devices;

means for monitoring a bit error rate of the ECC-encoded data written to the memory devices;

means for writing a first copy of the ECC-encoded data to a first address of the memory devices and, in parallel, writing a second copy of the ECC-encoded data to a second address of the memory devices; and

means for monitoring the bit error rates of the first and second copies of the ECC-encoded data and discarding either of the first and second copies having a higher bit error rate.

18. The method of claim 17, wherein the memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.

19. A solid-state mass storage device comprising a controller, a cache memory, and one or more non-volatile memory devices, the memory devices each being connected to an independent channel of the controller, the controller comprising:

an error checking and correction (ECC) engine for ECC-encoding data written from a host system to the storage device before writing the ECC-encoded data to the memory devices;

means for monitoring a bit error rate of the ECC-encoded data written to the memory devices and, if an average of the bit error rate of the ECC-encoded data increases beyond a threshold, switching to a parallel mode by writing a first copy of the ECC-encoded data to a first address of the memory devices and substantially simultaneously writing a second copy of the ECC-encoded data to a second address of the memory devices; and

means for monitoring the bit error rates of the first and second copies of the ECC-encoded data and discarding either of the first and second copies having a higher bit error rate.

20. The method of claim 19, wherein the non-volatile solid-state memory devices are chosen from the group comprising NAND flash, NOR flash, phase change memory, magnetoresistive memory, and resistive memory.