SEMICONDUCTOR ELEMENT-EMBEDDED WIRING SUBSTRATE

• US 20130026632A1
• Filed: 02/22/2011
• Published: 01/31/2013
• Est. Priority Date: 04/08/2010
• Status: Active Grant

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kikuchi, Katsumi, Yamamichi, Shintaro, Murai, Hideya, Mori, Kentaro, Nakashima, Yoshiki
• Granted Patent: US 8,710,639 B2
• Time in Patent Office: Days
• US Class Current: 257/753
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2223/6677 for antenna, e.g. antenna included within housing of semiconductor device
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45 of an individual wire connector
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 of an individual wire connector
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92 Specific sequence of method steps
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01037 : Rubidium [Rb]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01088 : Radium [Ra]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/07802 : not being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/0781 : being an ohmic electrical conductor
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H05K 1/0271 : Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 1/186 : manufactured by mounting on or connecting to patterned circuits before or during embedding
• CPC Class Codes: H05K 2201/10674 : Flip chip
• CPC Class Codes: H05K 2203/1469 : Circuit made after mounting or encapsulation of the components
• CPC Class Codes: H05K 3/4602 : characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Abstract

A wiring substrate in which a semiconductor element is built includes a semiconductor element; a peripheral insulating layer covering at least an outer circumferential side surface of this semiconductor element; and an upper surface-side wiring line provided on the upper surface side of the wiring substrate. The semiconductor element includes an internal terminal electrically connected to the upper surface-side wiring line on the upper surface side of the semiconductor element. This internal terminal includes a first conductive part exposed out of an insulating surface layer of the semiconductor element; an adhesion layer on this first conductive part; and a second conductive part on this adhesion layer. The adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of this second conductive part so as to surround the second conductive part.

Claims

1. A wiring substrate in which a semiconductor element is built, the wiring substrate comprising:

a semiconductor element;

a peripheral insulating layer covering at least an outer circumferential side surface of the semiconductor element; and

an upper surface-side wiring line provided on the upper surface side of the wiring substrate,

wherein the semiconductor element includes, on the upper surface side thereof, an internal terminal electrically connected to the upper surface-side wiring line,

the internal terminal includes;

a first conductive part exposed out of an insulating surface layer of the semiconductor element;

an adhesion layer on the first conductive part; and

a second conductive part on the adhesion layer, and

the adhesion layer covers an exposed surface of the first conductive part, and is formed on a portion of the insulating surface layer around the exposed surface of the first conductive part, and the adhesion layer extends around the outer side of an outer edge of the second conductive part so as to surround the second conductive part.

2. The wiring substrate according to claim 1, wherein the first conductive part, the adhesion layer and the second conductive part are respectively made of metal materials, and the insulating surface layer is made of a resin material.

3. The wiring substrate according to claim 1, wherein the adhesion layer is made of a metal material comprising a metal selected from the group consisting of Ti, W, Mo, Cr, V, Ta and Ni.

4. The wiring substrate according to claim 1, wherein the second conductive part is made of a metal material comprising a metal selected from the group consisting of gold, silver, copper, nickel, tin and palladium.

5. The wiring substrate according to claim 1, wherein the second conductive part is made of copper or a copper-based alloy.

6. The wiring substrate according to claim 1, wherein the semiconductor element includes a plurality of the internal terminals and includes adjacent internal terminals sharing an integrally-formed adhesion layer.

7. The wiring substrate according to claim 6, wherein the plurality of the internal terminals includes adjacent power supply terminals sharing an integrally-formed adhesion layer.

8. The wiring substrate according to claim 6, wherein the plurality of the internal terminals includes adjacent ground terminals sharing an integrally-formed adhesion layer.

9. The wiring substrate according to claim 1, wherein the second conductive part is shaped such that the peripheral length of the outer edge of the lower surface of the second conductive part in contact with the adhesion layer is greater than the peripheral length of the outer edge of the upper-surface of the second conductive part and that the peripheral length of the outer edge of a cross section of the second conductive part along the planar direction of the wiring substrate gradually increases in a direction from the upper surface side to the lower surface side thereof

10. The wiring substrate according to claim 1, wherein the first conductive part is part of a wiring line underneath the insulating surface layer and is a portion of the wiring line exposed out of an opening of the insulating surface layer.

11. The wiring substrate according to claim 1, wherein the first conductive part is a conductive part provided in an opening of the insulating surface layer.

12. The wiring substrate according to claim 1, further comprising a base insulating layer, wherein the semiconductor element and the peripheral insulating layer are provided on the upper surface side of the base insulating layer.

13. The wiring substrate according to claim 1, further comprising a protective insulating film covering the upper surface-side wiring line, wherein the protective insulating film includes an opening, and the wiring substrate comprises an external terminal made of a portion of the upper surface-side wiring line exposed in the opening, or an external terminal made of a conductive part provided in the opening.

14. The wiring substrate according to claim 1, further comprising an upper surface-side wiring structure layer including wiring lines and insulating layers alternately provided on the upper surface side of the wiring substrate,

wherein the uppermost layer-side insulating layer includes an opening, and the wiring substrate comprises an external terminal made of a portion of a wiring line exposed in the opening, or an external terminal made of a conductive part provided in the opening.

15. The wiring substrate according to claim 1, further comprising a lower surface-side wiring line provided on the lower surface side of the wiring substrate.

16. The wiring substrate according to claim 15, further comprising, in the peripheral insulating layer, a lateral-to-element via electrically connected to the upper surface-side wiring line and the lower surface-side wiring line.

17. The wiring substrate according to claim 15, further comprising a protective insulating film covering the lower surface-side wiring line, wherein the protective insulating film includes an opening, and the wiring substrate comprises an external terminal made of a portion of the lower surface-side wiring line exposed in the opening, or an external terminal made of a conductive part provided in the opening.

18. The wiring substrate according to claim 15, further comprising a lower surface-side wiring structure layer including wiring lines and insulating layers alternately provided on the lower surface side of the wiring substrate,

wherein the lowermost layer-side insulating layer includes an opening, and the wiring substrate comprises an external terminal made of a portion of a wiring line exposed in the opening, or an external terminal made of a conductive part provided in the opening.

19. The wiring substrate according to claim 1, further comprising a supporting substrate provided on the lower surface side of the wiring substrate.

20. The wiring substrate according to claim 1, wherein a noise-shielding circuit pattern is provided on the lower surface of the semiconductor element with an intervention of an insulating adhesive material.

21. The wiring substrate according to claim 1, wherein a potential-stabilizing circuit pattern is provided on the lower surface of the semiconductor element with an intervention of a conductive adhesive material.