SEMICONDUCTOR INTERATED CIRCUIT

• US 20130027121A1
• Filed: 03/05/2012
• Published: 01/31/2013
• Est. Priority Date: 07/26/2011
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: YOON, Sang-Sic
• Granted Patent: US 8,570,097 B2
• Time in Patent Office: Days
• US Class Current: 327/536
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence

Abstract

A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.

Claims

1. A semiconductor integrated circuit comprising:

a first pad configured to receive a first voltage;

a second pad configured to receive a second voltage;

an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode; and

an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.

2. The semiconductor integrated circuit of claim 1, wherein the internal voltage generation circuit comprises a pumping circuit which generates the third voltage whose voltage level is higher than the second voltage in response to a test mode signal.

3. The semiconductor integrated circuit of claim 1, wherein the internal voltage generation circuit comprises a down converter-type circuit which generates the third voltage whose voltage level is lower than the second voltage in response to a test mode signal.

4. The semiconductor integrated circuit of claim 3, wherein the internal voltage generation circuit comprises:

a first divider configured to generate a reference voltage by dividing the second voltage at a first division ratio;

a second divider configured to generate a feedback voltage by dividing the third voltage at a second division ratio;

a comparator configured to compare the feedback voltage with the reference voltage in response to the test mode signal; and

a driver configured to supply a terminal of the third voltage with the second voltage in response to an output signal of the comparator.

5. A semiconductor integrated circuit comprising:

a first pad configured to receive a first voltage;

a second pad configured to receive a second voltage having a higher voltage level than the first voltage;

an internal voltage generation circuit configured to generate a third voltage in response to the second voltage, wherein the third voltage has a lower voltage level than the first voltage during a normal mode and the same voltage level as the first voltage during a test mode; and

an internal circuit configured to perform a normal operation using the first voltage to the third voltage during the normal mode and perform a test operation using the second voltage and the third voltage during the test mode.

6. The semiconductor integrated circuit of claim 5, wherein terminals of the first voltage and the third voltage are electrically connected to each other.

7. The semiconductor integrated circuit of claim 5, wherein the internal voltage generation circuit comprises:

a first divider configured to generate a reference voltage in response to a test mode signal by dividing the second voltage at a first division ratio during the normal mode and at a second division ratio during the test mode;

a second divider configured to generate a feedback voltage by dividing the third voltage at a third division ratio;

a comparator configured to compare the feedback voltage with the reference voltage; and

a driver configured to supply a terminal of the third voltage with the second voltage in response to an output signal of the comparator.

8. The semiconductor integrated circuit of claim 7, wherein the first divider comprises a variable resistor whose resistance varies in response to the test mode signal.

9. The semiconductor integrated circuit of claim 7, wherein the first divider comprises:

a variable resistor disposed between terminals of the second voltage and the reference voltage, wherein a resistance value of the variable resistor is configured to vary in response to the test mode signal; and

a first resistor disposed between the terminal of the reference voltage and a terminal of a ground voltage.

10. The semiconductor integrated circuit of claim 9, wherein the variable resistor comprises:

a second resistor and a third resistor that are serially coupled between the terminals of the second voltage and the reference voltage; and

a bypass unit disposed in parallel to the second resistor and configured to serve as a bypass of the second resistor in response to the test mode signal.

11. The semiconductor integrated circuit of claim 10, wherein the bypass unit comprises a transistor which includes a gate for receiving the test mode signal, and a source and a drain that are coupled with the terminal of the second voltage and a node between the second and third resistors, respectively.

12. A semiconductor integrated circuit comprising:

a first pad configured to receive a first voltage in a normal mod of the semiconductor integrated circuit;

a second pad configured to receive a second voltage in the normal mode and a test mode of the semiconductor integrated circuit; and

an internal voltage generation circuit configured to generate a third voltage in response to the second voltage, wherein the third voltage has a lower voltage level than the first voltage during the normal mode and the same voltage level as the first voltage during the test mode.

13. The semiconductor integrated circuit of claim 12, wherein the internal voltage generation circuit is configured to supply the third voltage to compensate a drop in the first voltage during the normal mode.