METHOD AND APPARATUS FOR PARALLEL SCANNING AND DATA PROCESSING FOR TOUCH SENSE ARRAYS

• US 20130027346A1
• Filed: 09/28/2011
• Published: 01/31/2013
• Est. Priority Date: 07/27/2011
• Status: Active Grant

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Yarosh, Andriy, Sharamaga, Roman, Konovalov, Anton, Maharyta, Andriy, Ogirko, Roman, Pirogov, Oleksandr, Kremin, Viktor, Mohammed, Haneef
• Granted Patent: US 8,487,909 B2
• Time in Patent Office: Days
• US Class Current: 345/174
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

A parallel pipelining method of operation of a touch sense controller for processing data into a touch map is disclosed. A current full scan of response signals to at least one excitation of a touch sense array is received using a first thread of a processing device. The current full scan of response signals is processed using a second thread of the processing device to render a touch map corresponding to the touch sense array. A next full scan of response signals is received using the first thread. Receiving the next full scan and processing the current full scan are performed substantially simultaneously.

Claims

1. A method, comprising:

receiving a current full scan of response signals to at least one excitation of a touch sense array using a first thread of a processing device;

processing the current full scan of response signals using a second thread of the processing device to render a touch map corresponding to the touch sense array; and

receiving a next full scan of response signals using the first thread,

wherein the receiving the next full scan and processing the current full scan are performed substantially simultaneously.

2. The method of claim 1, wherein the first thread is a hardware scan thread of a sequencer and is not part of a central processing unit (CPU) of the processing device.

3. The method of claim 1, wherein the second thread is a hardware thread of a digital filter block (DFB) and is not part of a CPU of the processing device.

4. The method of claim 1, wherein the second thread is a software thread of a CPU of the processing device.

5. The method of claim 1, wherein processing the current full scan is initiated in response to receiving an interrupt corresponding to completion of receiving the current full scan.

6. The method of claim 1, wherein receiving the next full scan is initiated in response to receiving an interrupt corresponding to completion of processing of the current full scan.

7. The method of claim 4, wherein the first thread and the second thread are coordinated using semaphores or interrupts.

8. The method of claim 3, further comprising storing data corresponding to individual slots of response signals of the current or next full scan of response signals in corresponding single buffers.

9. The method of claim 8, further comprising combining the single buffers into a full sense array raw data buffer in order of slots.

10. The method of claim 9, further comprising directly transferring the combined data in the full sense array raw data buffer to memory using direct memory access (DMA).

11. A circuit, comprising:

a sequencer configured to receive a current full scan of response signals to at least one excitation of a touch sense array using a first thread and configured to receive a next full scan of response signals using the first thread; and

processing logic configured to process the current full scan of response signals using a second thread to render a touch map corresponding to the touch sense array,

wherein receiving the next full scan and processing the current full scan are performed substantially simultaneously.

12. The circuit of claim 11, wherein the first thread is a hardware scan thread of the sequencer and is not part of a central processing unit (CPU).

13. The circuit of claim 11, wherein the second thread is a hardware thread of a digital filter block (DFB) and is not part of a CPU.

14. The circuit of claim 11, wherein the second thread is a software thread of a CPU.

15. The circuit of claim 11, further comprising a CPU is configured to initiate processing the current full scan in response to an interrupt corresponding to completion of receiving the current full scan from the sequencer.

16. The circuit of claim 11, further comprising a CPU configured to initiate processing the next full scan in response to an interrupt corresponding to completion of receiving the current full scan from the sequencer.

17. The circuit of claim 11, further comprising:

a memory;

a direct memory access (DMA) controller coupled to the memory and the sequencer, wherein the DMA controller is configured to transfer data corresponding to individual response signals of the current or next full scan of response signals to corresponding single buffers in the memory.

18. The circuit of claim 17, wherein the DMA controller is further configured to combine the single buffers into a full sense array raw data buffer in order of slots in the memory.

19. An apparatus, comprising:

a processing device configured to detect a conductive object proximate to a touch sense array, wherein the processing device comprises;

a sequencer configured to receive a current full scan of response signals to at least excitation of a touch sense array using a first thread and configured to receive a next full scan of response signals using the first thread; and

processing logic configured to process the current full scan of response signals using a second thread to render a touch map corresponding to the touch sense array,

wherein receiving the next full scan and processing the current full scan are performed substantially simultaneously.

20. The apparatus of claim 19, wherein the second thread is a hardware thread of a DFB and is not part of a CPU of the processing device.