THIN FILM TRANSISTOR SUBSTRATE, LIQUID CRYSTAL DISPLAY HAVING SAME, AND METHOD OF MANUFACTURING THE SAME

• US 20130027627A1
• Filed: 07/09/2012
• Published: 01/31/2013
• Est. Priority Date: 07/25/2011
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: KANG, Su-Hyoung, Khang, Yoonho, Park, Sangho, Lee, Jungkyu, Chang, Chong Sup
• Granted Patent: US 9,484,420 B2
• Time in Patent Office: Days
• US Class Current: 349/46
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display apparatus includes a thin film transistor substrate, a substrate facing the thin film transistor substrate, and a liquid crystal layer. The thin film transistor substrate includes an insulating substrate, a gate electrode disposed on a surface of the insulating substrate, a gate insulating layer covering the gate electrode, a semiconductor layer disposed on the gate insulating layer, a source electrode disposed on the semiconductor layer, and a drain electrode disposed on the semiconductor layer and spaced apart from the source electrode. One of the source electrode and the drain electrode is spaced apart from the gate electrode in a plan view. The gate electrode includes a side surface inclined with respect to the surface of the insulating substrate and is partially overlapped with a portion of the source electrode or the drain electrode in a direction perpendicular to the side surface of the gate electrode.

Claims

1. A thin film transistor substrate comprising:

a substrate;

a gate electrode disposed on a surface of the substrate;

a gate insulating layer disposed on the gate electrode;

a semiconductor layer disposed on the gate insulating layer;

a first electrode disposed on the semiconductor layer; and

a second electrode disposed on the semiconductor layer and spaced apart from the first electrode, wherein the first electrode is spaced apart from the gate electrode when viewed in a direction perpendicular to the surface of the substrate, and the second electrode is partially overlapped with the gate electrode when viewed in the direction perpendicular to the surface of the substrate.

2. The thin film transistor substrate of claim 1, wherein the gate electrode comprises a side surface inclined with respect to the surface of the substrate.

3. The thin film transistor substrate of claim 2, wherein the first electrode is a source electrode and the second electrode is a drain electrode, or the first electrode is a drain electrode and the second electrode is a source electrode.

4. The thin film transistor substrate of claim 3, wherein the gate electrode is partially overlapped with a portion of the first electrode when viewed in a direction inclined with respect to the surface of the substrate.

5. The thin film transistor substrate of claim 4, wherein the overlapped area between the gate electrode and the first electrode has a width less than or equal to about 1 micrometer when viewed in the direction inclined with respect to the surface of the substrate.

6. The thin film transistor substrate of claim 1, wherein the gate electrode comprises a first concave portion, the semiconductor layer comprises a second concave portion corresponding to the first concave portion, and an end portion of the drain electrode is disposed in the first concave portion and the second concave portion.

7. A liquid crystal display comprising:

a first substrate comprising a pixel area, a first thin film transistor disposed in the pixel area, and a first pixel electrode connected to the first thin film transistor;

a second substrate facing the first substrate and comprising a common electrode; and

a liquid crystal layer disposed between the first substrate and the second substrate, the first thin film transistor comprising;

a first gate electrode disposed in the pixel area of the first substrate;

a gate insulating layer disposed on the first gate electrode;

a first semiconductor layer disposed on the gate insulating layer;

a first source electrode disposed on the first semiconductor layer;

a first drain electrode disposed on the first semiconductor layer and spaced apart from the first source electrode; and

a first pixel electrode connected to the first drain electrode,

wherein one of the first source electrode and the first drain electrode is spaced apart from the first gate electrode when viewed in a plan view.

8. The liquid crystal display of claim 7, wherein an upper portion of the first semiconductor layer is connected to the first source electrode and a lower portion of the first semiconductor layer is connected to the first drain electrode, or

the upper portion of the first semiconductor layer is connected to the first drain electrode and the lower portion of the first semiconductor layer is connected to the first source electrode.

9. The liquid crystal display of claim 7, wherein a side portion of the first semiconductor layer is a slanted portion that is inclined with respect to an upper portion of the first semiconductor layer.

10. The liquid crystal display of claim 7, wherein the first source electrode is adjacent to one end of a side portion of the first semiconductor layer and the first drain electrode is adjacent to the other end of the side portion of the first semiconductor layer.

11. The liquid crystal display of claim 7, wherein the first gate electrode comprises a side surface inclined with respect to a surface of the first substrate, the side surface of the gate electrode being substantially parallel to a side portion of the first semiconductor layer.

12. The liquid crystal display of claim 11, wherein the first gate electrode is partially overlapped with a portion of the first source electrode or the first drain electrode when viewed in a direction inclined with respect to the surface of the first substrate.

13. The liquid crystal display of claim 12, wherein the overlapped area between the first gate electrode and the first source electrode or the overlapped area between the first gate electrode and the first drain electrode has a width less than or equal to 1 micrometer when viewed in the direction inclined with respect to the surface of the first substrate.

14. The liquid crystal display of claim 7, further comprising a black matrix disposed between the first substrate and the first gate electrode, wherein the black matrix covers an area corresponding to the first source electrode and the first drain electrode.

15. The liquid crystal display of claim 7, wherein the first gate electrode comprises a first concave portion, the first semiconductor layer comprises a second concave portion corresponding to the first concave portion, and one end of the first drain electrode is disposed in the first concave portion and the second concave portion.

16. The liquid crystal display of claim 7, wherein the first substrate further comprises:

a plurality of gate lines extended in a first direction; and

a plurality of first data lines extended in a second direction crossing the first direction to define the pixel area with the gate lines.

17. The liquid crystal display of claim 16, wherein the first thin film transistor is connected to a corresponding gate line of the gate lines and a corresponding first data line of the first data lines.

18. The liquid crystal display of claim 16, further comprising:

a plurality of second data lines extended in the second direction and alternately arranged with the first data lines;

a second thin film transistor disposed in the pixel area and connected to a corresponding gate line of the gate lines and a corresponding second data line of the second data lines; and

a second pixel electrode connected to the second thin film transistor.

19. The liquid crystal display of claim 18, wherein the second thin film transistor comprises:

a second gate electrode disposed in the pixel area;

a gate insulating layer disposed on the second gate electrode;

a second semiconductor layer disposed on the gate insulating layer;

a second source electrode disposed on the second semiconductor layer; and

a second drain electrode disposed on the second semiconductor layer and spaced apart from the second source electrode, wherein

the second pixel electrode is connected to the second drain electrode, and

wherein one of the second source electrode and the second drain electrode is spaced apart from the second gate electrode when viewed in a direction perpendicular to the surface of the first substrate.

20. A method of manufacturing a thin film transistor substrate, comprising:

performing a first process using a first mask to form a gate electrode on a substrate;

forming a gate insulating layer on the gate electrode; and

performing a second process using a second mask to form an active layer, an ohmic contact layer, a source electrode, and a drain electrode on the gate insulating layer, wherein one of the source electrode and the drain electrode is spaced apart from the gate electrode when viewed in a plan view.

21. The method of claim 20, wherein the second mask comprises a first region corresponding to the source electrode, a second region corresponding to a channel between the source electrode and the drain electrode, and third region corresponding to the drain electrode, and a slit mask or a diffraction mask is applied to the second region.

22. The method of claim 21, wherein the second process comprises:

sequentially depositing a silicon layer, a silicon layer doped with an impurity, and a conductive layer on the gate insulating layer;

coating a photoresist on the conductive layer;

exposing and developing the photoresist using the second mask to form a first photoresist pattern;

sequentially etching the conductive layer, the doped silicon layer with the impurity, and the silicon layer using the first photoresist pattern as a mask to form an electrode pattern, an ohmic contact layer pattern, and the active layer;

ashing the first photoresist pattern to form a second photoresist pattern; and

etching the electrode pattern and the ohmic contact pattern using the second photoresist pattern as a mask to form the source electrode, the drain electrode, and the ohmic contact layer.

23. The method of claim 22, wherein the first photoresist pattern comprises a first photoresist portion having a first thickness on the first region, a second photoresist portion having a second thickness on the second region, and a third photoresist portion having a first thickness on the third region.

24. The method of claim 22, wherein the second photoresist pattern comprises a fourth photoresist portion having a third thickness on the first region, and a fifth photoresist portion having a third thickness on the third region.

25. The method of claim 20, wherein the gate electrode comprises a first concave portion, the semiconductor layer comprises a second concave portion corresponding to the first concave portion, and the drain electrode is disposed in the first concave portion and the second concave portion.

26. The method of claim 20, further comprising forming a black matrix to block a light passing through an area corresponding to the source electrode and the drain electrode.