APPARATUSES AND METHODS INCLUDING MEMORY ARRAY DATA LINE SELECTION

• US 20130028024A1
• Filed: 07/27/2011
• Published: 01/31/2013
• Est. Priority Date: 07/27/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Tanzawa, Toru
• Granted Patent: US 8,619,471 B2
• Time in Patent Office: Days
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/50 characterised by the boundary region between the core region and the peripheral circuit region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

Some embodiments include an apparatus having data lines coupled to memory cell strings and a selector configured to selectively couple one of the data lines to a node. The memory cell strings and the selector can be formed in the same memory array of the apparatus. Other embodiments including additional apparatus and methods are described.

Claims

1. An apparatus comprising:

data lines;

a node; and

a memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node.

2. The apparatus of claim 1, further comprising an additional node, wherein the selector includes a first multiplexer and a second multiplexer, the first multiplexer configured to selectively couple a selected data line of a first group of the data lines to the node, and the second multiplexer configured to selectively couple a selected data line of a second group of the data lines to the additional node.

3. The apparatus of claim 1, wherein the node is coupled to reference voltage.

4. The apparatus of claim 1, further comprising a substrate, wherein the selector includes a first transistor overlying the substrate and a second transistor overlying the first transistor.

5. The apparatus of claim 1, further comprising a substrate, wherein the selector includes a first gate overlying the substrate and a second gate overlying the first gate.

6. The apparatus of claim 1, further comprising a sense circuit configured to receive a signal from the node.

7. The apparatus of claim 6, further comprising a transistor, wherein the transistor includes a first node coupled to the node and a second node coupled to the sense circuit.

8. The apparatus of claim 7, wherein the transistor is configured to operate at a voltage greater than a supply voltage of the memory array.

9. The apparatus of claim 1, wherein the memory cell strings comprise U-shaped strings.

10. The apparatus of claim 1, wherein the selector includes a bias unit configured to couple the data lines to different voltages in different memory operations.

11. The apparatus of claim 10, wherein the bias unit includes a separate bias unit for each of the data lines.

12. The apparatus of claim 10, wherein the bias unit includes a same bias unit for each of the data lines.

13. An apparatus comprising:

a substrate;

a data line overlying the substrate;

a first body region coupled to the data line and having a length in a direction between the substrate and the data line, first gates located along the length of the first body region, and a first material between the first body region and the first gates, wherein at least a portion of the first material is configured to store information; and

a second body region coupled to the data line and having a length in the direction between the substrate and the data line, second gates located along the length of the second body region, and a second material between the second body region and the second gate, and no portion of the second material is configured to store information.

14. The apparatus of claim 13, wherein the second body region is configured to selectively form at least a portion of a conductive path between separate segments of the data line during an operation of the apparatus.

15. The apparatus of claim 14, wherein the conductive path includes a U-shaped conductive path.

16. The apparatus of claim 13, further comprising:

a third body region coupled to the data line, the third body region having a length in the direction between the substrate and the data line;

third gates located along the length of the third body region; and

a third material between the third body region and the third gates, wherein and no portion of the third material is configured to store information.

17. The apparatus of claim 16, further comprising a conductive line coupled between the second and third body regions, wherein each of the data line and the conductive line has a length in a same direction.

18. The apparatus of claim 16, further comprising:

a fourth body region coupled to the third body region, the fourth body region having a length in the direction between the substrate and the data line, and fourth gates being located along the length of the fourth body region; and

a conductive line coupled to the fourth body region, wherein the conductive line has a length in a first direction, the data line has a length in a second direction, and the second direction is substantially perpendicular to the first direction.

19. An apparatus comprising:

a first device level and a second device level;

a memory cell string including a first memory cell located at the first device level and a second memory cell located at the second device level;

a conductive line configured to exchange information with the memory cell string; and

a switching circuit configured to selectively exchange the information with a node, the circuit including a number of gates, the gates including a first gate located at the first device level and a second gate located at the second device level.

20. The apparatus of claim 19, wherein the first gate is coupled to the second gate.

21. The apparatus of claim 19, further comprising a third device level, wherein the circuit includes a third gate located at the third device level.

22. The apparatus of claim 19, wherein the memory cell string includes a number of gates equal to the number of gates of the circuit.

23. The apparatus of claim 19, wherein the memory cell and the switching circuit are formed from a same memory array.

24. The apparatus of claim 19, wherein the memory cell is formed from a memory array and the switching circuit are formed outside the memory array.

25. The apparatus of claim 23, further comprising a bias circuit, wherein the memory cell is formed from a memory array, and at least one of the switching circuit and the bias circuit is formed from the memory array.

26. The apparatus of claim 19, wherein a first group of gates among the gates of switching circuit is configured to receive a first signal, and a second group of gates among the gates of switching circuit is configured to receive a second signal different from the first signal.

27. The apparatus of claim 19, wherein the switching circuit includes elements configured to operate as pass elements.

28. The apparatus of claim 27, wherein the switching circuit includes a transistor coupled to the elements, and the transistor and the elements are configured to receive a same signal.

29. The apparatus of claim 27, wherein the switching circuit includes a transistor coupled to the elements, the transistor is configured to receive a first signal, and the elements are configured to receive a second signal different from the first signal.

30. An apparatus comprising:

a data line including a first segment and a second segment separated from the first segment;

a memory cell string coupled to the first segment, the memory cell string including a first body region having a length and first gates located along the length of the first body region; and

a switching circuit having a second body region coupled to the first segment and a third body region coupled to the second segment, a conductive line coupling the second body region to the third body region, and second gates located along a length of the first and second body regions.

31. The apparatus of claim 30, wherein the second body region, the third body region, and the conductive line are configured to selectively form a conductive path between the first and second segments during an operation of the apparatus.

32. The apparatus of claim 30, wherein the second body region, the third body region, and the conductive line comprise an identical material.

33. The apparatus of claim 32, wherein the identical material includes silicon.

34. The apparatus of claim 30, wherein the second gates are coupled together.

35. An apparatus comprising:

a first memory cell string including a first body region, first gates located along a length of the first body region, and a first material between the first gates and the first body region, wherein at least a portion of the first material is configured to store information;

a second memory cell string including a second body region, second gates located along a length of the second body region, and a second material between the gates and the second body region, wherein at least a portion of the second material is configured to store information;

a first data line coupled to the first memory cell string;

a second data line coupled to the second memory cell string; and

a selector configured to selectively couple one of the first and second data lines to a node, the selector including a third body region, third gates located along a length of the third body region, and a third material between the third gates and the third body region.

36. The apparatus of claim 35, wherein the third gates are coupled together.

37. The apparatus of claim 35, further comprising a substrate and a sense circuit formed in the substrate, wherein the selector includes at least one transistor overlying the substrate.

38. The apparatus of claim 37, further comprising an additional transistor coupled between the selector and the sense circuit, wherein the additional transistor is configured to operate at a voltage higher than a supply voltage of the apparatus.

39. An apparatus comprising:

a substrate;

a node;

a sense circuit coupled to the node, the sense circuit including at least a portion formed in the substrate;

data lines coupled to the node; and

a memory array formed over the substrate, the memory array including a first portion and a second portion, the first portion including memory cell strings coupled to the data lines, the second portion including a selector configured to selectively couple the data lines to the node.

40. The apparatus of claim 39, wherein the memory array further includes a third portion included in the selector, the third portion includes a bias circuit configured to selectively couple the data lines to a reference voltage.

41. The apparatus of claim 40, wherein each of the selector and the memory cell strings includes a body region coupled to one of the data lines, and the body region has a length in a direction between the substrate and the data lines.

42. A method comprising:

applying a same voltage to all gates of a circuit of an apparatus in a first operation of the apparatus, the circuit coupled between a first segment of a data line and a second segment of the data line of the apparatus, the first segment coupled to a memory cell string, the memory cell string including a first memory cell located at a first device level of the device and a second memory cell located at a second device level of the apparatus; and

applying the same voltage to each of the gates of the circuit in a second operation of the apparatus.

43. The method of claim 42, wherein the first operation includes a read operation.

44. The method of claim 43, wherein the second operation includes a write operation.

45. The method of claim 44, further comprising:

applying a first voltage to a first group of gates among the gates in a third operation; and

applying a second voltage to a second group of gates among the gates in the third operation, wherein the first and second voltages have different values.

46. The method of claim 45, wherein the third operation includes an initialization operation.

47. The method of claim 44, further comprising:

applying another voltage to each of the gates in a third operation of the apparatus.

48. The method of claim 47, wherein the third operation includes an erase operation.

49. The method of claim 42, wherein the voltage includes zero volts.

50. The method of claim 42, wherein the voltage has a positive value.

51. The method of claim 42, further comprising:

coupling the first segment to a first voltage if a value of the voltage applied to the gates is zero volts in the first operation.

52. The method of claim 51, further comprising:

coupling the first segment to a second voltage if the voltage applied to the gates is zero volts in the second operation.

53. The method of claim 52, wherein the first operation includes a read operation, and the second voltage has a value greater than a value of the first voltage.