Systems, Methods, and Apparatuses for Negative-Charge-Pump-Based Antenna Switch Controllers Utilizing Battery Supplies

• US 20130029614A1
• Filed: 07/29/2011
• Published: 01/31/2013
• Est. Priority Date: 07/29/2011
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Changhyuk, Cha, Jeongwon, Ahn, Minsik, Lee, Chang-Ho, Chang, Jae Joon, Woo, Wyangmyong
• Application Number:
  US13/194,325
• Publication Number:
  US 20130029614A1
• Time in Patent Office: Days
• US Class Current: 455/83
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

Systems, methods, and apparatuses may provide for antenna switch controllers. An example antenna switch controller may include: a plurality of antenna switches commonly connected to one or more antennas, where each of the plurality of antenna switches includes a plurality of stacked transistors, where one of the plurality of antenna switches is enabled when transmitting or receiving one or more radio frequency (RF) signals via the one or more antennas; a voltage generator that receives an external supply voltage from a battery, where the voltage generator generates an internal supply voltage, where the internal supply voltage remains constant despite fluctuations in the external supply voltage from the battery; a clock buffer that generates clock signals from the constant internal supply voltage; and a charge pump that receives the clock signals and generates a constant negative voltage, where the constant negative voltage is for biasing of one or more of the plurality of antenna switches that are disabled.

Claims

1. A CMOS antenna switch controller, comprising:

a plurality of antenna switches commonly connected to one or more antennas, wherein each of the plurality of antenna switches includes a plurality of stacked transistors, wherein one of the plurality of antenna switches is enabled when transmitting or receiving one or more radio frequency (RF) signals via the one or more antennas;

a voltage generator that receives an external supply voltage from a battery, wherein the voltage generator generates an internal supply voltage, wherein the internal supply voltage remains constant despite fluctuations in the external supply voltage from the battery;

a clock buffer that generates clock signals from the constant internal supply voltage; and

a charge pump that receives the clock signals and generates a constant negative voltage, wherein the constant negative voltage is for biasing of one or more of the plurality of antenna switches that are disabled.

2. The CMOS antenna switch of claim 1, wherein the constant negative voltage biases one or more respective gates of the plurality of stacked transistors when the respective antenna switch is disabled.

3. The CMOS antenna switch of claim 2, wherein the respective antenna switch is disabled when one of the other plurality of antenna switches is in a transmit (TX) mode or a receive (RX) mode.

4. The CMOS antenna switch of claim 1, further comprising:

at least one output driver, wherein the at least one output driver is configured to receive the constant negative voltage and to output the constant negative voltage for biasing the one or more of the plurality of antenna switches when disabled.

5. The CMOS antenna switch of claim 4, wherein the at least one output driver includes a level shifter for shifting a positive control voltage to the constant negative signal that is output for biasing the one or more of the plurality of antenna switches that are disabled.

6. The CMOS antenna switch of claim 4, wherein the voltage generator, the clock buffer, and the charge pump form a main negative charge pump block, and further comprising:

a sub negative charge block pump block that includes;

a second voltage generator that receives the external supply voltage from the battery, wherein the second voltage generator generates a second internal supply voltage, wherein the second internal supply voltage remains constant despite fluctuations in the external supply voltage from the battery;

a second clock buffer that generates second clock signals from the second constant internal supply voltage; and

a second charge pump that receives the second clock signals and generates a second constant negative voltage, wherein the second constant negative voltage is for biasing transistors of the output driver to enable the first constant negative voltage to be output by the output driver.

7. The CMOS antenna switch of claim 4, wherein the at least one output driver is further configured to supply a zero voltage or a constant positive voltage for biasing one or more of the plurality of antenna switches.

8. The CMOS antenna switch of claim 7, wherein the constant positive voltage provided for biasing the one or more of the plurality of antenna switches that are enabled

9. The CMOS antenna switch of claim 7, wherein the zero voltage is utilized during a receive (RX) mode for biasing one or more of the antenna switches that are not operating.

10. The CMOS antenna switch of claim 4, wherein the at least one output driver includes a plurality of PMOS transistors and NMOS transistors configured to respond to control signals by enabling the at least one output driver to output the constant negative voltage, the zero voltage, or the constant positive voltage.

11. The CMOS antenna switch of claim 10, further comprising:

a logic decoder for providing control signals to the at least one output driver, the control signals associated with a receive (RX) mode or a transmit (TX) for one or more of the plurality of antenna switches.

12. The CMOS antenna switch of claim 1, wherein the antenna switches, the voltage generator, the clock buffer, and the charge pump are fabricated using one or more silicon-based processes.

13. The CMOS antenna switch of claim 1, wherein the one or more silicon-based processes includes a silicon-on-insulator (SOI) process.

14. A method for a CMOS switch controller, comprising:

providing a plurality of antenna switches commonly connected to one or more antennas, wherein each of the plurality of antenna switches includes a plurality of stacked transistors, wherein one of the plurality of antenna switches is enabled when transmitting or receiving one or more radio frequency (RF) signals via the one or more antennas;

receiving, by the voltage generator, an external supply voltage from a battery, and generating a respective internal supply voltage, wherein the internal supply voltage remains constant;

generating, by a clock buffer, clock signals from the constant internal supply voltage; and

receiving, by a charge pump, the clock signals and generating a constant negative voltage, wherein the constant negative voltage is for biasing one or more of the plurality of antenna switches that are disabled.

15. The method of claim 14, further comprising:

providing at least one output driver, wherein the at least one output driver is configured to receive the constant negative voltage and to output the constant negative voltage for biasing the one or more of the plurality of antenna switches when disabled.

16. The method of claim 15, wherein the at least one output driver includes a level shifter for shifting a positive control voltage to the constant negative signal that is output for biasing the one or more of the plurality of antenna switches that are disabled.

17. The method of claim 15, wherein the voltage generator, the clock buffer, and the charge pump form a main negative charge pump block, and wherein the method further includes:

providing a sub negative charge block pump block that includes;

a second voltage generator that receives the external supply voltage from the battery, wherein the second voltage generator generates a second internal supply voltage, wherein the second internal supply voltage remains constant despite fluctuations in the external supply voltage from the battery;

a second clock buffer that generates second clock signals from the second constant internal supply voltage; and

a second charge pump that receives the second clock signals and generates a second constant negative voltage, wherein the second constant negative voltage is for biasing transistors of the output driver to enable the first constant negative voltage to be output by the output driver.

18. The method of claim 15, wherein the at least one output driver includes a plurality of PMOS transistors and NMOS transistors configured to respond to control signals by enabling the at least one output driver to output the constant negative voltage, the zero voltage, or the constant positive voltage.

19. The method of claim 18, further comprising:

providing, by a logic decoder, control signals to the at least one output driver, the control signals associated with a receive (RX) mode or a transmit (TX) for one or more of the plurality of antenna switches.

20. The method of claim 14, wherein the constant negative voltage biases one or more respective gates of the plurality of stacked transistors when the respective antenna switch is disabled.