METHOD AND APPARATUS FOR TLB SHOOT-DOWN IN A HETEROGENEOUS COMPUTING SYSTEM SUPPORTING SHARED VIRTUAL MEMORY

• US 20130031333A1
• Filed: 07/26/2011
• Published: 01/31/2013
• Est. Priority Date: 07/26/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lantz, Philip R., Mallick, Asit K., Crossland, James B., Navale, Aditya, Neiger, Gilbert, Anderson, Andrew V., Sankaran, Rajesh M., Koker, Altug
• Granted Patent: US 9,916,257 B2
• Time in Patent Office: Days
• US Class Current: 711/207
• CPC Class Codes: G06F 12/1027 using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/303 In peripheral interface, e.g. I/O adapter or channel
• CPC Class Codes: G06F 2212/682 Multiprocessor TLB consistency
• CPC Class Codes: G06F 2212/683 Invalidation

Abstract

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

Claims

1. A method for efficient TLB shoot-downs in a multi-core system with heterogeneous devices sharing virtual memory, the method comprising:

receiving one or more Process Address Space Identifier (PASID) state update requests from one or more respective requesting devices of a plurality of heterogeneous devices in the multi-core system;

performing an atomic modification of a PASID state corresponding to a first of the one or more PASID state update requests;

performing a lazy invalidation check for the corresponding PASID state; and

sending a PASID state update response to a requesting device corresponding to said first of the one or more PASID state update requests.

2. The method of claim 1 further comprising:

processing a TLB shoot-down from an operating system in the multi-core system.

3. The method of claim 2 wherein processing a TLB shoot-down comprises:

invalidating an IOTLB entry.

4. The method of claim 3 wherein processing a TLB shoot-down comprises:

invalidating a device TLB entry of one of the plurality of heterogeneous devices.

5. The method of claim 2 wherein processing a TLB shoot-down comprises:

reading a PASID state entry; and

setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

6. The method of claim 5 wherein processing a TLB shoot-down comprises:

invalidating an IOTLB entry if the active reference count in the PASID state entry is not zero; and

invalidating a device TLB entry of one of the plurality of heterogeneous devices if the active reference count in the PASID state entry is not zero.

7. The method of claim 5 wherein setting a lazy-invalidate field in the PASID state entry is performed using a locked compare-and-exchange instruction.

8. The method of claim 1 wherein the atomic modification of the PASID state comprises:

decrementing an active reference count if the first PASID state update request indicates a deactivation update.

9. The method of claim 1 wherein the atomic modification of the PASID state comprises:

reading a PASID state entry including a lazy-invalidate field;

incrementing an active reference count if the first PASID state update request indicates an activation update; and

clearing the lazy-invalidate field if the first PASID state update request indicates an activation update.

10. The method of claim 9 further comprising:

invalidating an IOTLB entry if the lazy-invalidate field included in the PASID state entry read was set; and

setting a device synchronization flag for the first PASID state update request if the lazy-invalidate field included in the PASID state entry read was set and the first PASID state update request indicates an activation update.

11. An apparatus comprising:

a TLB to store a plurality of virtual address translation entries; and

a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference state and a lazy-invalidation state,

said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in a multi-core system and to read the lazy-invalidation state of the first PASID state entry,

the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

12. The apparatus of claim 11 wherein the atomic modification of the first PASID state comprises:

reading the first PASID state entry including the lazy-invalidate field;

incrementing an active reference count if the first PASID state update request indicates an activation update; and

clearing the lazy-invalidate field if the first PASID state update request indicates an activation update.

13. The apparatus of claim 11 wherein the memory management unit responsive at least in part to the lazy-invalidation state read is further to:

invalidate a TLB virtual address translation entry corresponding to the first PASID state entry; and

set a synchronization flag for the PASID state update response sent to the device.

14. The apparatus of claim 11 wherein the memory management unit is further to:

process a TLB shoot-down from an operating system in the multi-core system.

15. The apparatus of claim 14 wherein processing a TLB shoot-down comprises:

invalidating a TLB virtual address translation entry.

16. The apparatus of claim 14 wherein processing a TLB shoot-down comprises:

causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated.

17. The apparatus of claim 14 wherein processing a TLB shoot-down comprises:

reading a PASID state entry; and

setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

18. The apparatus of claim 17 wherein processing a TLB shoot-down comprises:

invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and

causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.

19. The apparatus of claim 17 wherein setting a lazy-invalidate field in the PASID state entry is performed using a locked compare-and-exchange instruction.

20. A multi-core processor comprising:

a first plurality of homogeneous processing cores;

a heterogeneous processing device;

a TLB to store a plurality of virtual address translation entries; and

a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference state and a lazy-invalidation state,

said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in the multi-core processor and to read the lazy-invalidation state of the first PASID state entry,

the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

21. The multi-core processor of claim 20 wherein the atomic modification of the first PASID state entry comprises:

reading the first PASID state entry including the lazy-invalidate field;

incrementing an active reference count if the first PASID state update request indicates an activation update; and

clearing the lazy-invalidate field if the first PASID state update request indicates an activation update.

22. The multi-core processor of claim 20 wherein the memory management unit is further to process a TLB shoot-down from an operating system.

23. The multi-core processor of claim 22 wherein processing a TLB shoot-down comprises:

reading a PASID state entry; and

setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

24. The multi-core processor of claim 23 wherein processing a TLB shoot-down comprises:

invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and

causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.

25. The multi-core processor of claim 23 wherein setting a lazy-invalidate field in the PASID state entry is performed using a locked compare-and-exchange instruction.

26. A multi-core system comprising:

a memory to store a plurality of page tables containing virtual address translation entries;

a first plurality of homogeneous processing cores;

a heterogeneous processing device;

a TLB to store a plurality of the virtual address translation entries; and

a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference state and a lazy-invalidation state,

said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in the multi-core system and to read the lazy-invalidation state of the first PASID state entry,

the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

27. The multi-core system of claim 26 wherein the memory management unit is further to:

process a TLB shoot-down from an operating system in the multi-core system.

28. The multi-core system of claim 27 wherein processing a TLB shoot-down comprises:

causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated.

29. The multi-core system of claim 27 wherein processing a TLB shoot-down comprises:

reading a PASID state entry; and

setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

30. The multi-core system of claim 29 wherein processing a TLB shoot-down comprises:

invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and

causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.