Post-Write Read in Non-Volatile Memories Using Comparison of Data as Written in Binary and Multi-State Formats

• US 20130031431A1
• Filed: 10/24/2011
• Published: 01/31/2013
• Est. Priority Date: 07/28/2011
• Status: Abandoned Application

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Sharon, Eran, Alrod, Idan
• Application Number:
  US13/280,217
• Publication Number:
  US 20130031431A1
• Time in Patent Office: Days
• US Class Current: 714/719
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/3481 Circuits or methods to verify correct programming of nonvolatile memory cells whilst programming is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

Techniques for a post-write read are presented. In an exemplary embodiment, host data is initially written into the non-volatile memory in binary form, such as a non-volatile binary cache. It is then subsequently written from the binary section into a multi-state non-volatile section of the memory. After being written in multi-state format, pages of data from a multi-state block can then be checked against there source pages in the binary section to verify the quality of the multi-state write. This process can be performed on the memory device itself, without transferring the pages out to the controller.

Claims

1. A method of operating a non-volatile memory system including a controller circuit and a memory circuit connected to the controller circuit over a bus structure, the memory circuit having a first section of non-volatile memory storing data in binary format and a second section of non-volatile memory storing data in an N-bit per cell multi-state format, where N is an integer two or greater, the method comprising:

receiving from a host a plurality of at least N pages of data at the controller circuit;

transferring the plurality of pages from the controller circuit to the memory circuit over the bus structure;

writing the plurality of pages on a corresponding plurality of word lines in the first section of the memory circuit;

writing N pages of data from the corresponding N word lines of the first section of memory on to a single word line of the second section of the memory circuit;

reading a first of the pages of data as written from the second section of the memory and as written from the first section of the memory;

performing on the memory circuit a comparison of first page of data as read from the second section of the memory with the first page of data as read from the first section;

based on the comparison, determining whether the first page of data as written into the second section is potentially corrupted.

5. The method of claim 1, wherein the second section is formed of a plurality of erase blocks, and wherein said reading the first of the pages of data as written from the second section of the memory is performed subsequent the writing of the complete block to which the first page was written.

6. The method of claim 5, the method further comprising:

marking the block to which the first page was written as defective in a memory management structure for the memory system.

8. The method of claim 1, wherein said performing a comparison includes:

performing an exclusive OR operation of the first page of data as read from the second section of the memory with the first page of data as read from the first section; and

wherein said determining includes counting a number of 1s resulting from the exclusive OR operation.

2. The method of 1, wherein said determining is performed on the memory circuit.

3. The method of 2, further comprising:

in response to determining that the first page of data as written into the second section is potentially corrupted, sending an indication thereof from the memory circuit to the controller circuit.

4. The method of 3, further comprising:

performing a further determination on the controller circuit of whether the first page of data as written into the second section is potentially corrupted; and

in response to further determining that the first page of data as written into the second section is potentially corrupted, rewriting the first page of data in to the second section of memory.

7. The method of 1, further comprising:

transferring the comparison from the memory circuit to the controller circuit over the bus structure, wherein said determining is performed on the controller circuit.

9. A method of operating a non-volatile memory system including a controller circuit and a memory circuit connected to the controller circuit over a bus structure, the memory circuit having a first section of non-volatile memory storing data in binary format and a second section of non-volatile memory storing data in an N-bit per cell multi-state format, where N is an integer two or greater, the method comprising:

receiving from a host a plurality of at least N pages of data at the controller circuit;

transferring the plurality of pages from the controller circuit to the memory circuit over the bus structure;

writing the plurality of pages on a corresponding plurality of word lines in the first section of the memory circuit;

writing the pages of data from the first section of memory in to the second section of memory, where, for each word line written in the second section, N pages of data from N corresponding word lines of the first section of memory are written on to a single word line of the second section;

reading a first plurality of pages of data as written from the second section of the memory and as written from the first section of the memory and reading said first plurality of pages as written from the first section of the memory;

performing on the memory circuit a combined comparison of the first plurality of pages of data as read from the second section of the memory with the first plurality of pages of data as read from the first section;

based on the combined comparison, determining whether the first plurality of pages as written into the second section includes a potentially corrupted page of data.

10. The method of claim 9, wherein forming a combined comparison includes:

performing an exclusive OR operation of the first plurality of pages of data as read from the second section of the memory and the first plurality of pages of data as read from the first section.

11. The method of claim 10, wherein said determining includes counting a number of 1s resulting from the exclusive OR operation.

12. The method of claim 10, wherein performing the exclusive OR operation includes:

for each of the first plurality of pages of data, performing an exclusive OR operation of the page as read from the second section of memory with the page as read from the first section of memory; and

subsequently performing, for each of the first plurality of pages of data, an exclusive OR operation of the exclusive OR operations of the page as read from the second section of memory with the page as read from the first section of memory.

13. The method of claim 10, wherein performing the exclusive OR operation includes:

for all of the first plurality of pages of data, performing an exclusive OR operation of the pages as read from the second section of memory;

for all of the first plurality of pages of data, performing an exclusive OR operation of the pages as read from the first section of memory; and

subsequently performing an exclusive OR operation of the exclusive OR operation of the pages as read from the second section of memory with the exclusive OR operation of the pages as read from the first section of memory.

14. The method of claim 9, wherein first plurality of pages of data includes multiple pages written to the same word line of the second section.

15. The method of claim 9, wherein the second section is formed of a plurality of erase blocks, and wherein said first plurality of pages correspond to the data content of a block of the second section and said writing the pages of data from the first section of memory in to the second section of memory writes a complete block of the second section.

16. The method of claim 9, wherein said determining is performed on the memory circuit.

17. The method of 16, further comprising:

in response to determining that t the first plurality of pages as written into the second section includes a potentially corrupted page of data, sending an indication thereof from the memory circuit to the controller circuit.

18. The method of 17, wherein the second section is formed of a plurality of erase blocks and the method further comprises:

performing a further determination on the controller circuit of whether the first plurality of pages as written into the second section includes a potentially corrupted page of data;

in response to further determining that the first plurality of pages as written into the second section includes a potentially corrupted page of data, rewriting the data of the block to which the first plurality of pages was written into another block of the second section of memory.

19. The method of claim 18, wherein said reading the first plurality of pages from the second section of the memory is performed subsequent the writing of a complete block with the first plurality of pages.

20. The method of claim 19, the method further comprising:

marking said complete block to which the first page was written as defective in a memory management structure for the memory system.

21. The method of 9, further comprising:

transferring the combined comparison from the memory circuit to the controller circuit over the bus structure, wherein said determining is performed on the controller circuit.