Non-volatile Memory Cell Having A High K Dielectric And Metal Gate

• US 20130032872A1
• Filed: 07/26/2012
• Published: 02/07/2013
• Est. Priority Date: 08/05/2011
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Su, Chien-Sheng, Kotov, Alexander
• Granted Patent: US 8,883,592 B2
• Time in Patent Office: Days
• US Class Current: 257/319
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.

Claims

1. A non-volatile memory cell comprising,

a substantially single crystalline semiconductor substrate of a first conductivity type;

a first region of a second conductivity type along a surface of the substrate;

a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region;

a channel region between the first region and the second region in the substrate along the surface thereof;

said channel region having a first portion and a second portion, with the first portion adjacent to the first region;

a word line having a bottom and a side, with the bottom spaced apart from the first portion of the channel region;

said word line comprising a polysilicon portion and a metal portion with the metal portion along the bottom of the word line closest to the first portion of the channel region;

a high K dielectric insulator between the bottom of the word line and the first portion of the channel region;

a floating gate spaced apart from the second portion of the channel region and spaced apart and adjacent to the word line;

a coupling gate spaced apart from the floating gate and spaced apart and adjacent to the word line; and

an erase gate spaced apart from the second region, said erase gate adjacent to and spaced apart from the coupling gate and the floating gate.

2. The memory cell of claim 1 wherein said metal portion of said word line extends along the side of the word line and is between the polysilicon portion and the floating gate and the coupling gate.

3. The memory cell of claim 2 wherein said high K dielectric insulator extends along the side of the word line and is between the metal portion and the floating gate and the coupling gate.

4. The memory cell of claim 3 wherein said high K dielectric insulator comprises a material selected from hafnium dioxide, hafnium silicate, zirconium dioxide and zirconium silicate.

5. The memory cell of claim 4 wherein said metal portion comprises titanium nitride.

6. The memory cell of claim 5 wherein said metal portion further comprises a capping layer.

7. The memory cell of claim 6 wherein said capping layer comprises lanthanum oxide.

8. The memory cell of claim 3 wherein said erase gate has a bottom and a side and comprises a polysilicon portion and a metal portion with the metal portion along the side of the erase gate between the erase gate and the floating gate and the coupling gate and along the bottom of the erase gate closest to the second region;

a high K dielectric insulator between the metal portion of the erase gate along the side thereof and the floating gate and the coupling gate and between the metal portion along the bottom of the erase gate and the second region.

9. The memory cell of claim 8 wherein said high K dielectric insulator comprises a material selected from hafnium dioxide, hafnium silicate, zirconium dioxide and zirconium silicate.

10. The memory cell of claim 9 wherein said metal portion comprises titanium nitride.

11. The memory cell of claim 10 wherein said metal portion further comprises a capping layer.

12. The memory cell of claim 11 wherein said capping layer comprises lanthanum oxide.

13. A method of forming a non-volatile memory cell on a substantially single crystalline semiconductor substrate of a first conductivity type, having a first region of a second conductivity along a surface of the substrate, said method comprising:

forming a stacked gate structure on the surface of said substrate, adjacent to the first region, said staked gate structure having two sidewalls, a first sidewall and a second sidewall, said stacked gate structure comprising a floating gate insulated from the surface of the substrate, and a coupling gate on said floating gate and insulated therefrom;

depositing a layer of high K dielectric material over said stacked gate structure and over said substrate;

said high K dielectric material being formed along the first sidewall and the second sidewall and is adjacent thereto, and on the surface of said substrate adjacent to the stacked gate structure;

depositing a metal layer immediately adjacent to the high K dielectric layer, said metal layer formed along the first sidewall and the second sidewall and is immediately adjacent to the high K dielectric layer, and on said high K dielectric layer over the surface of said substrate adjacent to the stacked gate structure;

forming a first polysilicon gate immediately adjacent to the metal layer on one side of the stacked gate structure, and over the substrate, and insulated therefrom;

forming a second polysilicon gate immediately adjacent to the metal layer on another side of the stacked gate structure, and over the first region and insulated therefrom; and

forming a second region in said substrate immediately adjacent to the first polysilicon gate.

14. The method of claim 13 wherein said first polysilicon gate and second polysilicon gate are formed in the same step.

15. The method of claim 14 wherein said high K dielectric material comprises a material selected from hafnium dioxide, hafnium silicate, zirconium dioxide and zirconium silicate.

16. The method of claim 15 wherein said metal layer comprises titanium nitride.

17. The method of claim 16 wherein said metal layer further comprises a capping layer.

18. The method of claim 17 wherein said capping layer comprises lanthanum oxide.

19. The method of claim 14 wherein said stacked gate structure further having a top surface, between the first sidewall and the second sidewall, wherein said high K dielectric material is deposited on said top surface, and said metal layer is deposited on the high K dielectric material on the top surface, and

wherein said first polysilicon gate and second polysilicon gate are formed in the same step by depositing a layer of polysilicon over the top surface of the stacked gate structure, adjacent to the first and second sidewalls of the stacked gate structure, and on the substrate.

20. The method of claim 19 further comprising a removal step to remove the polysilicon, the high K dielectric material and the metal layer on the top surface of the stacked gate structure to form the first polysilicon gate and the second polysilicon gate.