Non-volatile Memory Cell Having A High K Dielectric And Metal Gate
First Claim
1. A non-volatile memory cell comprising,a substantially single crystalline semiconductor substrate of a first conductivity type;
- a first region of a second conductivity type along a surface of the substrate;
a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region;
a channel region between the first region and the second region in the substrate along the surface thereof;
said channel region having a first portion and a second portion, with the first portion adjacent to the first region;
a word line having a bottom and a side, with the bottom spaced apart from the first portion of the channel region;
said word line comprising a polysilicon portion and a metal portion with the metal portion along the bottom of the word line closest to the first portion of the channel region;
a high K dielectric insulator between the bottom of the word line and the first portion of the channel region;
a floating gate spaced apart from the second portion of the channel region and spaced apart and adjacent to the word line;
a coupling gate spaced apart from the floating gate and spaced apart and adjacent to the word line; and
an erase gate spaced apart from the second region, said erase gate adjacent to and spaced apart from the coupling gate and the floating gate.
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Abstract
A non-volatile memory including a substrate of a first conductivity type with first and second spaced apart regions formed therein of a second conductivity type with a channel region therebetween. A polysilicon metal gate word line is positioned over a first portion of the channel region and spaced apart therefrom by a high K dielectric layer. The metal portion of the word line is immediately adjacent to the high K dielectric layer. A polysilicon floating gate is immediately adjacent to and spaced apart from the word line, and positioned over and insulated from another portion of the channel region. A polysilicon coupling gate is positioned over and insulated from the floating gate. A polysilicon erase gate is positioned on another side of and insulated from the floating gate, positioned over and insulated from the second region, and immediately adjacent to but spaced apart from another side of the coupling gate.
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Citations
20 Claims
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1. A non-volatile memory cell comprising,
a substantially single crystalline semiconductor substrate of a first conductivity type; -
a first region of a second conductivity type along a surface of the substrate; a second region of the second conductivity type along the surface of the substrate, spaced apart from the first region; a channel region between the first region and the second region in the substrate along the surface thereof;
said channel region having a first portion and a second portion, with the first portion adjacent to the first region;a word line having a bottom and a side, with the bottom spaced apart from the first portion of the channel region;
said word line comprising a polysilicon portion and a metal portion with the metal portion along the bottom of the word line closest to the first portion of the channel region;a high K dielectric insulator between the bottom of the word line and the first portion of the channel region; a floating gate spaced apart from the second portion of the channel region and spaced apart and adjacent to the word line; a coupling gate spaced apart from the floating gate and spaced apart and adjacent to the word line; and an erase gate spaced apart from the second region, said erase gate adjacent to and spaced apart from the coupling gate and the floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of forming a non-volatile memory cell on a substantially single crystalline semiconductor substrate of a first conductivity type, having a first region of a second conductivity along a surface of the substrate, said method comprising:
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forming a stacked gate structure on the surface of said substrate, adjacent to the first region, said staked gate structure having two sidewalls, a first sidewall and a second sidewall, said stacked gate structure comprising a floating gate insulated from the surface of the substrate, and a coupling gate on said floating gate and insulated therefrom; depositing a layer of high K dielectric material over said stacked gate structure and over said substrate;
said high K dielectric material being formed along the first sidewall and the second sidewall and is adjacent thereto, and on the surface of said substrate adjacent to the stacked gate structure;depositing a metal layer immediately adjacent to the high K dielectric layer, said metal layer formed along the first sidewall and the second sidewall and is immediately adjacent to the high K dielectric layer, and on said high K dielectric layer over the surface of said substrate adjacent to the stacked gate structure; forming a first polysilicon gate immediately adjacent to the metal layer on one side of the stacked gate structure, and over the substrate, and insulated therefrom; forming a second polysilicon gate immediately adjacent to the metal layer on another side of the stacked gate structure, and over the first region and insulated therefrom; and forming a second region in said substrate immediately adjacent to the first polysilicon gate. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification