PACKAGED MICROELECTRONIC ELEMENTS HAVING BLIND VIAS FOR HEAT DISSIPATION

• US 20130032934A1
• Filed: 08/01/2011
• Published: 02/07/2013
• Est. Priority Date: 08/01/2011
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: Tessera, Inc. (Adeia Inc.)
• Inventors: Fisch, David Edward
• Granted Patent: US 8,618,647 B2
• Time in Patent Office: Days
• US Class Current: 257/698
• CPC Class Codes: H01L 21/4882 Assembly of heatsink parts
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/14519 including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/17519 including bump connectors providing primarily thermal dissipation
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06565 the devices having the same size and there being no auxiliary carrier between the devices
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5384 Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

System and method for thermal management in a multi-chip packaged device. A microelectronic unit is disclosed, and includes a semiconductor element having a top surface and a bottom surface remote from the top surface. A semiconductor device including active elements is located adjacent to the top surface. Operation of the semiconductor device generates heat. Additionally, one or more first blind vias extend from the bottom surface and partially into a thickness of the semiconductor element. In that manner, the blind via does not contact or extend to the semiconductor device (defined as active regions of the semiconductor element, and moreover, is electrically isolated from the semiconductor device. A thermally conductive material fills the one or more first blind vias for heat dissipation. Specifically, heat generated by the semiconductor device thermally conducts from the semiconductor element, and is further distributed, transferred and/or dissipated through the one or more first blind vias to other connecting components.

Claims

1. A microelectronic unit, comprising:

a semiconductor element having a top surface and a bottom surface remote from said top surface;

a semiconductor device adjacent to said top surface;

one or more first blind vias extending from said bottom surface and partially into a thickness of said semiconductor element; and

a thermally conductive material filling said one or more first blind vias for heat dissipation.

2. The microelectronic unit of claim 1, further comprising:

an insulating layer adjacent to said bottom surface, said insulating layer having a rear surface remote from said bottom surface, wherein each of said one or more first blind vias extends from said rear surface and through the insulating layer and into said semiconductor element.

3. The microelectronic unit of claim 1, further comprising:

electrically conductive material placed in contact with said thermally conductive material, wherein said thermally conductive material is also electrically conductive, and wherein said electrically conductive material is configured such that adjacent electrically conductive material are interconnected in a mesh structure.

4. The microelectronic unit of claim 3, wherein said electrically conductive material comprises:

a plurality of solder balls.

5. The microelectronic unit of claim 3, further comprising:

a through via extending through said microelectronic unit;

second thermally conductive material filling said through via; and

second electrically conductive material connected to said mesh and to said second thermally conductive material.

6. The microelectronic unit of claim 3, further comprising:

a second semiconductor element having a second top surface and a second bottom surface remote from said second top surface;

a second semiconductor device adjacent to said second top surface;

a dielectric element adjacent to said second semiconductor device, said dielectric element having a front surface remote from said second semiconductor device;

one or more second blind vias extending from said front surface and partially into a thickness of said dielectric element;

second thermally conductive material filling each of said one or more second blind vias; and

second electrically conductive material connected to said second thermally conductive material, wherein said semiconductor device and said second semiconductor device are stacked in the same orientation such that that said electrically conductive material and said second electrically conductive material are in contact to form a second mesh structure.

7. The microelectronic unit of claim 3, further comprising:

a second semiconductor element having a second top surface and a second bottom surface remote from said second top surface;

a second semiconductor device adjacent to said top surface;

one or more second blind vias extending from said second bottom surface and partially into a thickness of said second semiconductor element;

second thermally conductive material filling each of said one or more second blind vias for heat dissipation; and

second electrically conductive material connected to said second thermally conductive material, wherein said semiconductor device and said second semiconductor device are stacked in opposing orientation such that that said electrically conductive material and said second electrically conductive material are in contact to form a mesh structure.

8. The microelectronic unit of claim 1, further comprising:

a package including said semiconductor device, wherein said mesh is electrically coupled to one or more terminals leading externally to said package.

9. The microelectronic unit of claim 1, further comprising:

a barrier metal lining at least one of said one or more first blind vias and separating said thermally conductive material from said semiconductor element.

10. The microelectronic unit of claim 1, wherein said semiconductor device comprises a DRAM array.

11. A multi-chip packaged unit, comprising:

a plurality of semiconductor chips stacked and joined together, at least one chip comprising;

a semiconductor element having a top surface and a bottom surface remote from said top surface;

a semiconductor device adjacent to said top surface;

one or more first blind vias extending from said bottom surface and partially into a thickness of said semiconductor element; and

a thermally conductive material filling each of said one or more first blind vias for heat dissipation; and

electrically conductive material placed in contact with said thermally conductive material filling said one or more first blind vias, and configured such that adjacent electrically conductive material are interconnected to form a mesh structure.

12. The microelectronic unit of claim 11, wherein said electrically conductive material comprises:

a plurality of solder balls.

13. The microelectronic unit of claim 11, further comprising:

one or more through vias each extending through a corresponding semiconductor chip and filled with corresponding second thermally conductive material; and

a plurality of second electrically conductive material electrically coupling together said one or more through vias, wherein each second electrically conductive material is connected to a corresponding second thermally conductive material and to a corresponding mesh structure.

14. The microelectronic unit of claim 11, wherein each chip further comprises:

an insulating layer adjacent to said bottom surface, said insulating layer having a rear surface remote from said bottom surface, wherein said one or more first blind vias extends from said rear surface and through the insulating layer and into said semiconductor element.

15. The microelectronic unit of claim 11, wherein each chip further comprises:

a dielectric element adjacent said semiconductor device, said dielectric element having a front surface remote from said semiconductor device;

one or more second blind vias extending from said front surface and partially into a thickness of said dielectric element;

a second thermally conductive material filling each of said one or more second blind vias; and

second electrically conductive material connected with said second thermally conductive material, and configured such that adjacent second electrically conductive material are interconnected to form a second mesh structure; and

wherein adjacent chips that are stacked are configured such that a corresponding first mesh structure is connected to a corresponding second mesh structure.

16. The microelectronic unit of claim 11, wherein adjacent chips that are stacked are configured such that corresponding first mesh structures are connected together.

17. A method for performing thermal management in a microelectronic unit, comprising:

forming a semiconductor element having a first surface and a second surface remote from said first surface;

forming a semiconductor device adjacent to said first surface;

forming a blind via extending from said second surface and partially into a thickness of said semiconductor element; and

filling said blind via with a thermally conductive material for heat dissipation.

18. The method of claim 17, further comprising:

forming an electrically conductive material at said second surface, wherein said electrically conductive material is conductively connected with said thermally conductive material.

19. The method of claim 17, further comprising:

forming an insulating layer adjacent to said second surface, said insulating layer having a rear surface remote from said second surface;

extending said blind via through said insulating layer; and

forming an electrically conductive material at said rear surface, wherein said electrically conductive material is conductively connected with said thermally conductive material.

20. The method of claim 17, further comprising:

forming a plurality of blind vias extending from said second surface and partially into said thickness of said semiconductor element;

filling said plurality of blind vias with said thermally conductive material;

forming a plurality of solder balls at said second surface, wherein each solder ball is conductively connected with thermally conductive material of a corresponding blind via; and

configuring spacing of said plurality of blind vias such that adjacent solder balls are in contact to form a conductive mesh.

21. The method of claim 20, further comprising:

forming a dielectric layer adjacent said semiconductor device;

forming a through via extending from said second surface through said semiconductor element and said dielectric layer;

filling said through via with a second electrically conductive material; and

connecting said second electrically conductive material with said conductive mesh.