Memory Buffers and Modules Supporting Dynamic Point-to-Point Connections
First Claim
1. A memory module comprising:
- a module interface having module data-group ports, to communicate data as respective data groups, and a module command port to receive memory-access commands;
a first memory device including a first device data-group port;
a second memory device including a second device data-group port; and
a signal buffer coupled between the module interface and each of the first and second memory devices, the signal buffer supporting;
a first mode in which the signal buffer, responsive to the memory-access commands, communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports; and
a second mode in which the signal buffer, responsive to the memory-access commands, alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
1 Assignment
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Accused Products
Abstract
A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
34 Citations
40 Claims
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1. A memory module comprising:
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a module interface having module data-group ports, to communicate data as respective data groups, and a module command port to receive memory-access commands; a first memory device including a first device data-group port; a second memory device including a second device data-group port; and a signal buffer coupled between the module interface and each of the first and second memory devices, the signal buffer supporting; a first mode in which the signal buffer, responsive to the memory-access commands, communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports; and a second mode in which the signal buffer, responsive to the memory-access commands, alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory buffer comprising:
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a controller interface having controller data-group ports to communicate data as respective data groups, and a first command port to receive memory-access commands; a first memory-device interface including a first device data-group port; and a second memory-device interface including a second device data-group port; wherein the memory buffer supports; a first mode in which the memory buffer, responsive to the memory-access commands, communicates the data group associated with each of the first and second device data-group ports via a respective one of the controller data-group ports; and a second mode in which the memory buffer, responsive to the memory-access commands, alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the controller data-group ports. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
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31. A memory module comprising:
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a signal buffer having a module data interface, a module command interface, a first memory data interface, a second memory data interface, a first memory command interface, and a second memory command interface; a first memory device receiving commands from the first memory command interface and communicating memory data with the first memory data interface; and a second memory device receiving commands from the second memory command interface and communicating memory data with the second memory data interface; the signal buffer having a state machine to direct memory-access commands received at the module data interface to either the first or the second memory device, and to convey memory data associated with each memory-access command between the first and second memory data interfaces and the module data interface.
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32. A method for configuring a data width of a memory module, the memory module having memory devices and module data-group ports to communicate respective data groups, the method comprising:
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sensing a value indicative of the data width; responsive to a first value indicative of a first data width, coupling each module-data group port to a respective one of the memory devices; and responsive to a second value indicative of a second data width, alternatively coupling a subset of the module-data group ports to a first or a second subset of the memory devices. - View Dependent Claims (33, 34, 35, 36, 37, 38, 39, 40)
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Specification