Data processing apparatus and method for powering down a cache

• US 20130036270A1
• Filed: 08/04/2011
• Published: 02/07/2013
• Est. Priority Date: 08/04/2011
• Status: Abandoned Application

• Current Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Arm Limited (SoftBank Group Corp.), Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Paver, Nigel Charles, Dreslinski, Ronald G., Saidi, Ali
• Application Number:
  US13/137,313
• Publication Number:
  US 20130036270A1
• Time in Patent Office: Days
• US Class Current: 711/128
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A data processing apparatus is provided comprising a processing device, and an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data. Dirty way indication circuitry is configured to generate an indication of the degree of dirty data stored in each way. Further, staged way power down circuitry is responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data. This approach provides a particularly quick and power efficient technique for powering down the cache in a plurality of stages.

Claims

1. A data processing apparatus comprising:

a processing device;

an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device;

dirty way indication circuitry configured to generate an indication of the degree of dirty data stored in each way; and

staged way power down circuitry responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data.

2. A data processing apparatus as claimed in claim 1, wherein the dirty way indication circuitry comprises degree way dirty checking circuitry configured, for each of a number of the ways, to generate an indication of the degree of dirty data stored in that way having regard to the dirty fields of that way.

3. A data processing apparatus as claimed in claim 1, wherein the dirty way indication circuitry is configured to infer the degree of dirty data stored in each way from information about how the ways of the cache are used.

4. A data processing apparatus as claimed in claim 3, wherein the dirty way indication circuitry is configured to infer the degree of dirty data stored in each way based on an allocation policy used to allocate data into the ways of the cache.

5. A data processing apparatus as claimed in claim 1, wherein each said way portion comprises one of said cache lines, such that a dirty field is provided for each cache line.

6. A data processing apparatus as claimed in claim 1, wherein during at least one stage of said plurality of stages, the staged way power down circuitry is configured to power down any ways containing no dirty data.

7. A data processing apparatus as claimed in claim 1, wherein:

during at least one stage of said plurality of stages, the staged way power down circuitry is configured to initiate a dirty data migration process, during which dirty data in at least one targeted way that is still powered is moved to at least one donor way that is still powered to seek to remove all dirty data from said at least one targeted way; and

the staged way power down circuitry is configured to power down any targeted way that has no dirty data following the dirty data migration process.

8. A data processing apparatus as claimed in claim 1, wherein:

during a final stage of said plurality of stages, the staged way power down circuitry is configured to initiate a clean operation in respect of any remaining ways that are still powered, and to then power down those remaining ways.

9. A data processing apparatus as claimed in claim 2, further comprising:

cache way allocation circuitry configured to allocate new write data into the N-way set associative cache, in the event that the new write data is marked as dirty data, the cache way allocation circuitry being configured to reference the degree way dirty checking circuitry in order to preferentially allocate that new write data to a way already containing dirty data.

10. A data processing apparatus as claimed in claim 9, wherein in the event that there are multiple ways that can store the new write data without evicting dirty data already stored in the cache, the cache way allocation circuitry is configured to allocate the new write data to that way from amongst said multiple ways that currently stores the most dirty data having regard to said indications produced by the degree way dirty checking circuitry.

11. A data processing apparatus as claimed in claim 9, wherein said cache way allocation circuitry is configured, in the event that the new write data is marked as dirty data, to allocate that new write data to a way chosen from a predetermined subset of ways reserved for allocation of dirty data.

12. A data processing apparatus as claimed in claim 1, further comprising:

cache way allocation circuitry configured to allocate new write data into the N-way set associative cache, in the event that the new write data is marked as dirty data, the cache way allocation circuitry being configured to employ an allocation policy that allocates that new write data to a way chosen from a predetermined subset of ways reserved for allocation of dirty data.

13. A data processing apparatus as claimed in claim 12, wherein the cache way allocation circuitry is configured to select between said allocation policy and a default allocation policy based on configuration data.

14. A data processing apparatus as claimed in claim 1, further comprising:

dirty data migration circuitry, responsive to a migration condition, to initiate a dirty data migration process, during which dirty data in at least one targeted way is moved to at least one donor way to seek to remove all dirty data from said at least one targeted way.

15. A data processing apparatus as claimed in claim 14, wherein said migration condition is triggered by a period of low activity.

16. A data processing apparatus as claimed in claim 14, wherein said migration condition is triggered by a signal asserted from said staged way power down circuitry whilst powering down at least a subset of the ways of the N-way set associative cache.

17. A data processing apparatus as claimed in claim 1, wherein said at least one predetermined condition comprises an indication that the processing device is being powered down, and the staged way power down circuitry is configured to power down all of the ways of the N-way set associative cache.

18. A data processing apparatus as claimed in claim 1, wherein said at least one predetermined condition comprises a condition giving rise to an expectation that the processing device will be powered down within a predetermined timing window, and the staged way power down circuitry is configured to power down only a subset of the ways of the N-way set associative cache.

19. A data processing apparatus as claimed in claim 1, further comprising:

an additional processing device having a lower performance than said processing device;

said at least one predetermined condition comprising an indication that the processing device is being powered down in order to transfer processing to the additional processing device.

20. A data processing apparatus as claimed in claim 19, wherein said N-way set associative cache is shared with said additional processing device, and the staged way power down circuitry is configured to power down only a subset of the ways of the N-way set associative cache, in order to provide a reduced size cache for use by the additional processing device.

21. A data processing apparatus as claimed in claim 1, further comprising:

an additional processing device having a higher performance than said processing device;

said at least one predetermined condition comprising an indication that the processing device is being powered down in order to transfer processing to the additional processing device.

22. A data processing apparatus as claimed in claim 1, wherein said at least one predetermined condition comprises a condition indicating a period of low cache utilisation, and the staged way power down circuitry is configured to power down a subset of the ways of the N-way set associative cache in order to reduce energy consumption of the cache.

23. A data processing apparatus as claimed in claim 2, wherein each degree way dirty checking circuitry comprises counter circuitry for maintaining a counter which is incremented as each dirty field of the associated way is set and which is decremented as each dirty field of the associated way is cleared.

24. A data processing apparatus as claimed in claim 2, wherein each degree way dirty checking circuitry comprises adder circuitry for performing an addition operation in respect of the values held in each dirty field of the associated way in order to identify the number of dirty fields that are set.

25. A data processing apparatus as claimed in claim 2, wherein each degree way dirty checking circuitry is configured to perform an approximation function based on the dirty fields of the associated way in order to provide an output indicative of the degree of dirty data stored in that associated way.

26. A data processing apparatus as claimed in claim 2, wherein said degree way dirty checking circuitry is provided for each way of the N-way set associative cache.

27. A cache structure comprising:

an N-way set associative cache for access by a processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device;

dirty way indication circuitry configured to generate an indication of the degree of dirty data stored in each way; and

staged way power down circuitry responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data.

28. A method of powering down an N-way set associative cache within a data processing apparatus, the N-way set associative cache being configured for access by a processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device, the method comprising:

for each way, generating an indication of the degree of dirty data stored in that way; and

responsive to at least one predetermined condition, powering down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the indication of the degree of dirty data stored in each way being referenced during the powering down process in order to seek to power down ways with less dirty data before ways with more dirty data.

29. A data processing apparatus comprising:

processing means;

an N-way set associative cache means for access by the processing means, each way comprising a plurality of cache line means for temporarily storing data for a subset of memory addresses of a memory means, and a plurality of dirty field means, each dirty field means being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache means without that modification being made to the equivalent data held in the memory means;

dirty way indication means for generating an indication of the degree of dirty data stored in each way; and

staged way power down means, responsive to at least one predetermined condition, for powering down at least a subset of the ways of the N-way set associative cache means in a plurality of stages, the staged way power down means for referencing the dirty way indication means in order to power down ways with less dirty data before ways with more dirty data.