Data processing apparatus and method for powering down a cache
First Claim
1. A data processing apparatus comprising:
- a processing device;
an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device;
dirty way indication circuitry configured to generate an indication of the degree of dirty data stored in each way; and
staged way power down circuitry responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data.
2 Assignments
0 Petitions
Accused Products
Abstract
A data processing apparatus is provided comprising a processing device, and an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data. Dirty way indication circuitry is configured to generate an indication of the degree of dirty data stored in each way. Further, staged way power down circuitry is responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data. This approach provides a particularly quick and power efficient technique for powering down the cache in a plurality of stages.
-
Citations
29 Claims
-
1. A data processing apparatus comprising:
-
a processing device; an N-way set associative cache for access by the processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device; dirty way indication circuitry configured to generate an indication of the degree of dirty data stored in each way; and staged way power down circuitry responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
-
-
27. A cache structure comprising:
-
an N-way set associative cache for access by a processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device; dirty way indication circuitry configured to generate an indication of the degree of dirty data stored in each way; and staged way power down circuitry responsive to at least one predetermined condition, to power down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the staged way power down circuitry being configured to reference the dirty way indication circuitry in order to seek to power down ways with less dirty data before ways with more dirty data.
-
-
28. A method of powering down an N-way set associative cache within a data processing apparatus, the N-way set associative cache being configured for access by a processing device, each way comprising a plurality of cache lines for temporarily storing data for a subset of memory addresses of a memory device, and a plurality of dirty fields, each dirty field being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache without that modification being made to the equivalent data held in the memory device, the method comprising:
-
for each way, generating an indication of the degree of dirty data stored in that way; and responsive to at least one predetermined condition, powering down at least a subset of the ways of the N-way set associative cache in a plurality of stages, the indication of the degree of dirty data stored in each way being referenced during the powering down process in order to seek to power down ways with less dirty data before ways with more dirty data.
-
-
29. A data processing apparatus comprising:
-
processing means; an N-way set associative cache means for access by the processing means, each way comprising a plurality of cache line means for temporarily storing data for a subset of memory addresses of a memory means, and a plurality of dirty field means, each dirty field means being associated with a way portion and being set when the data stored in that way portion is dirty data, dirty data being data that has been modified in the cache means without that modification being made to the equivalent data held in the memory means; dirty way indication means for generating an indication of the degree of dirty data stored in each way; and staged way power down means, responsive to at least one predetermined condition, for powering down at least a subset of the ways of the N-way set associative cache means in a plurality of stages, the staged way power down means for referencing the dirty way indication means in order to power down ways with less dirty data before ways with more dirty data.
-
Specification