METHOD FOR ALLOCATING ADDRESSES TO DATA BUFFERS IN DISTRIBUTED BUFFER CHIPSET

• US 20130036287A1
• Filed: 10/18/2011
• Published: 02/07/2013
• Est. Priority Date: 08/03/2011
• Status: Active Grant

• Current Assignee: Montage Technology Company Limited
• Original Assignee: Montage Technology Company Limited
• Inventors: Ma, Qingjiang, Chu, Huaixiang
• Granted Patent: US 9,201,817 B2
• Time in Patent Office: Days
• US Class Current: 711/170
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

The present invention relates to a method for allocating addresses to data buffers in a distributed buffer chipset, in which a memory controller informs a central buffer of the beginning of address allocation through a Command/Address channel (CA), and then the central buffer informs through a data control channel all the data buffers of preparing for receiving address parameters through respective data channels, and in this way, each data buffer receives and latches the respective address parameter from the memory controller through the respective data, thus avoiding the defect in the prior art that the size of the data buffer and the size of the entire distributed buffer chipset is bigger as several address pins need to be additionally configured in each data buffer to allocate the respective address parameter.

Claims

1. A method for allocating addresses to data buffers in a distributed buffer chipset, applied in a distributed buffer chipset controlled by a memory controller, wherein the distributed buffer chipset at least comprises a central buffer connected to the memory controller through one Command/Address channel (CA) and a plurality of data buffers respectively connected to the memory controller through respective data channels, and the data buffers are connected to the central buffer through sharing one data control channel, the method for allocating addresses to data buffers in a distributed buffer chipset comprising:

1) at the memory controller, sending an address allocation start signal to the central buffer through the CA, and sending respective address parameters to the corresponding data buffers through the data channels;

2) at the central buffer, sending the received address allocation start signal to all the data buffers through the data control channel, so as to inform all the data buffers of preparing for receiving the address parameters through the respective data channels; and

3) at each data buffer, correspondingly receiving and latching the address parameter through the respective data.

2. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 1, wherein the address parameter is formed by a specific number of address configuration values, and the address configuration value is a binary number.

3. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 2, wherein a calculation formula of the specific number is as follows:

the value of N is a minimum integer value satisfying an inequality 2^N≧

M, where N is the specific number, and M is the number of the data buffers in the distributed buffer chipset.

4. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 3, wherein the step 1) further comprises:

1-1) at the memory controller, presetting designated time and a specific number; and

1-2) at the memory controller, sending an address allocation start signal to the central buffer through the CA, resetting and staring the time, sending respective address configuration values to the corresponding data buffers through the data channels, and maintaining a state of driving the corresponding address configuration values before the time reaches the preset designated time.

5. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 4, wherein the step 3) further comprises:

3-1) at each data buffer, correspondingly receiving the address configuration value through the respective data channel and latching the address configuration value by the data buffer;

3-2) at the memory controller, when the time reaches the preset designated time, stopping sending the address configuration values, subtracting 1 from the preset specific number, and judging whether the specific number is 0 after the subtraction of 1, if yes, performing step 3-3);

otherwise, returning to the step 1-2); and

3-3) at each data buffer, according to a precedence order of the latched address configuration values, sequentially concatenating the address configuration values to form a respective address parameter with the first latched address configuration value as the lowest bit and with the last latched address configuration value as the highest bit, and ending the allocation process.

6. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 5, wherein the designated time is set to ensure that the data buffer has enough time to receive and latch the address configuration value after receiving the address allocation start signal.

7. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 5, wherein the data channel has multiple signal lines respectively connected to a corresponding number of data pins of the corresponding data buffer.

8. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 7, wherein the step 1-1) further comprises:

sending the address configuration value through anyone of all the signal lines of the data channel.

9. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 8, wherein the step 3-1) further comprises:

at each data buffer, once a certain data pin of the data buffer receives the address configuration value, latching the address configuration value.

10. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 7, wherein the step 1-1) further comprises:

designating a certain data pin of the data buffer to receive the address configuration value, and sending the same address configuration value through all the signal lines of the data channel, so as to ensure that the designated data pin of the data buffer receives the address configuration value.

11. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 3, wherein the step 1) further comprises:

1-a) at the memory controller, presetting a specific number; and

1-b) at the memory controller, sending an address allocation start signal to the central buffer through the CA, sending respective address configuration values to the corresponding data buffers through the data channels, and maintaining a state of driving the corresponding address configuration values.

12. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 11, wherein the step 3) further comprises:

3-a) at each data buffer, correspondingly receiving the address configuration value through the respective data channel, latching the address configuration value, and sending a completion notification signal to the memory controller by the data buffer;

3-b) at the memory controller, after receiving the completion notification signals sent from all the data buffers, stopping sending the address configuration values, subtracting 1 from the preset specific number, and judging whether the specific number is 0 after the subtraction of 1, if yes, performing step 3-c);

otherwise, returning to the step 1-b); and

3-c) at each data buffer, according to a precedence order of the latched address configuration values, sequentially concatenating the address configuration values to form a respective address parameter with the first latched address configuration value as the lowest bit and with the last latched address configuration value as the highest bit, and ending the allocation process.

13. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 12, wherein the data channel has multiple signal lines respectively connected to a corresponding number of data pins of the corresponding data buffer.

14. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 13, wherein the step 1-a) further comprises:

sending the address configuration value through any one of all the signal lines of the data channel.

15. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 14, wherein the step 3-a) further comprises:

at each data buffer, once a certain data pin of the data buffer receives the address configuration value, latching the address configuration value.

16. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 13, wherein the step 1-a) further comprises:

designating a certain data pin of the data buffer to receive the address configuration value, and sending the same address configuration value through all the signal lines of the data channel, so as to ensure that the designated data pin of the data buffer receives the address configuration value.

17. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 3, wherein the data channel has multiple signal lines respectively connected to a corresponding number of data pins of the corresponding data buffer.

18. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 17, wherein the step 1) further comprises:

at the memory controller, sending all the address configuration values of the address parameter to the data buffer at the same time according to a certain order through the specific number of signal lines in each data channel in a manner of one signal line corresponding to one address configuration value.

19. The method for allocating addresses to data buffers in a distributed buffer chipset as in claim 18, wherein the step 3) further comprises:

at each data buffer, correspondingly receiving the address configuration values through its data pins, sequentially latching the received address configuration values according to the order, and finally obtaining the respective address parameter by the data buffer.