SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

• US 20130037795A1
• Filed: 07/18/2012
• Published: 02/14/2013
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: SUNAMURA, Hiroshi, INOUE, Naoya, KANEKO, Kishou
• Granted Patent: US 8,664,769 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An element using a semiconductor layer is formed between wiring layers and, at the same time, a gate electrode is formed using a conductive material other than a material for wirings. A first wiring is embedded in a surface of a first wiring layer. A gate electrode is formed over the first wiring. The gate electrode is coupled to the first wiring. The gate electrode is formed by a process different from a process for the first wiring. Therefore, the gate electrode can be formed using a material other than a material for the first wiring. Further, a gate insulating film and a semiconductor layer are formed over the gate electrode.

Claims

1. A semiconductor device comprising:

a first wiring layer having a first wiring;

a second wiring layer formed over the first wiring layer and having a second wiring;

a gate electrode located between the first wiring and the second wiring in a thickness direction, containing a material different from that of the first wiring, and coupled to the first wiring;

a gate insulating film located over the gate electrode;

a semiconductor layer located over the gate insulating film; and

a first via embedded into the second wiring layer and coupling the semiconductor layer with the second wiring.

2. The semiconductor device according to claim 1, comprising the two second wirings,

wherein the two second wirings are coupled to the semiconductor layer through the first vias which are different from each other, and

wherein the two first vias are disposed on the opposite sides from each other through the center of the gate electrode in a plan view.

3. The semiconductor device according to claim 2,

wherein the semiconductor layer is larger than the gate electrode in a plan view, and

wherein the center of the two first vias is not overlapped with the gate electrode.

4. The semiconductor device according to claim 1, comprising:

a third wiring formed in the first wiring layer;

a fourth wiring formed in the second wiring layer; and

a second via embedded into the second wiring layer and coupling the third wiring with the fourth wiring.

5. The semiconductor device according to claim 4,

wherein the third wiring has a configuration similar to that of the first wiring,

wherein the fourth wiring has a configuration similar to that of the second wiring, and

wherein the second via has a configuration similar to that of the first via.

6. The semiconductor device according to claim 1, comprising:

a diffusion prevention film formed over the first wiring layer;

an opening formed in the diffusion prevention film and located over the first wiring; and

a barrier metal film located inside the opening and coupling the gate electrode with the first wiring.

7. The semiconductor device according to claim 1, comprising:

a diffusion prevention film formed between the first wiring layer and the second wiring layer; and

an opening formed in the diffusion prevention film and located over the first wiring,

wherein the gate electrode is formed at least inside the opening.

8. The semiconductor device according to claim 7, wherein the gate electrodes are formed inside the opening and over the diffusion prevention film located around the opening.

9. The semiconductor device according to claim 7, wherein the gate electrode is located only inside the opening.

10. The semiconductor device according to claim 9, wherein an upper surface of the gate electrode and an upper surface of the diffusion prevention film form the same plane.

11. The semiconductor device according to claim 7, comprising a barrier metal film located inside the opening and coupling the gate electrode with the first wiring.

12. The semiconductor device according to claim 6, comprising a protective insulating film located over the diffusion prevention film,

wherein the openings are formed in the protective insulating film and the diffusion prevention film.

13. The semiconductor device according to claim 12, wherein the protective insulating film is formed using a material whose dielectric constant is lower than that of a silicon oxide or formed of a porous film of such a material.

14. The semiconductor device according to claim 1,

wherein the first wiring layer and the second wiring layer are formed over a substrate, and

wherein the semiconductor device comprises a first transistor formed over the substrate.

15. The semiconductor device according to claim 14, wherein the first transistor is overlapped with the semiconductor layer in a plan view.

16. The semiconductor device according to claim 2, wherein the gate electrode, the gate insulating film, and the semiconductor layer form a second transistor.

17. The semiconductor device according to claim 16, comprising at least the two second transistors,

wherein at least the two transistors have different combinations of materials for the gate electrode, the gate insulating film, and the semiconductor layer.

18. The semiconductor device according to claim 17, wherein at least the two second transistors have the same electric conductive types of channels and have different threshold voltages from each other.

19. The semiconductor device according to claim 16, comprising:

an internal circuit; and

a power supply pad formed in an uppermost wiring layer of the multi-layer wiring layer and supplying a power supply voltage to the internal circuit,

wherein the internal circuit is coupled to the power supply pad through the second transistor.

20. The semiconductor device according to claim 1,

wherein the semiconductor layer has a source and a drain,

wherein the source is shorted with the gate electrode, and

wherein the source, the drain, the gate insulating film, and the gate electrode form a diode.

21. The semiconductor device according to claim 20, comprising:

an internal circuit;

an I/O pad formed in an uppermost layer of the multi-layer wiring layer and supplying signals to the internal circuit; and

a ground pad formed in the uppermost wiring layer and supplying a ground potential to the internal circuit,

wherein the diode is provided between the I/O pad and the ground pad such that a direction from the I/O pad toward the ground pad is a forward direction.

22. The semiconductor device according to claim 1, wherein the gate electrode, the gate insulating film, and the semiconductor layer form a capacitance element.

23. The semiconductor device according to claim 1,

wherein the first wiring is a Cu wiring, and

wherein the gate electrode comprises Ti, Ta, W, TiN, TaN, WN films, a compound containing Co or W, a film made by introducing at least one of C and O to one of the above, or a stacked film made by stacking two or more kinds of these films.

24. The semiconductor device according to claim 1, wherein the gate insulating film includes a silicon oxide film, a silicon nitride film, or an oxide film having at least one of Hf, Zr, Al, Ti, and Ta.

25. The semiconductor device according to claim 1, wherein the semiconductor layer is an oxide semiconductor layer.

26. The semiconductor device according to claim 25, wherein the oxide semiconductor layer is an InGaZnO layer, an InZnO layer, a ZnO layer, a ZnAlO layer, a ZnCuO layer, an NiO layer, an NiO₂ layer, an SnO layer, or a CuO layer.

27. The semiconductor device according to claim 1, comprising a hard mask film formed over the semiconductor layer and having the same planar shape as that of the semiconductor layer.

28. The semiconductor device according to claim 27, wherein the hard mask film is comprised of the same material as that of the diffusion prevention film and has a layer having the same thickness as that of the diffusion prevention film.

29. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first wiring layer having a first wiring over a semiconductor substrate;

forming, over the first wiring layer, a first gate electrode, a first gate insulating film located over the first gate electrode, and a first semiconductor layer located over the first gate insulating film; and

forming, over the first wiring layer and over the first semiconductor layer, a second wiring layer having a second wiring,

wherein the first gate electrode is coupled to the first wiring and the second wiring is coupled to the first semiconductor layer.

30. The method for manufacturing the semiconductor device according to claim 29, comprising, between the step of forming the first wiring layer and the step of forming the first gate electrode, the first gate insulating film, and the first semiconductor layer, the steps of:

forming a diffusion prevention film over the first wiring layer; and

forming, in the diffusion prevention film, a first opening located over the first wiring,

wherein, in the step of forming the first gate electrode, the first gate electrode is coupled with the first wiring by overlapping the first gate electrode with the first opening in a plan view.

31. The method for manufacturing the semiconductor device according to claim 30, comprising, between the step of forming the first opening and the step of forming the first gate electrode, a step of:

forming a barrier metal film in the first opening.

32. The method for manufacturing the semiconductor device according to claim 31, wherein the step of embedding the barrier metal film into the first opening includes the steps of:

forming barrier metal films in the first opening and over the diffusion prevention film; and

removing the barrier metal film located over the diffusion prevention film by a CMP method.

33. The method for manufacturing the semiconductor device according to claim 32, comprising the steps of:

allowing, after the step of embedding the barrier metal film into the first opening, an upper surface of the barrier metal film to be located lower than an upper end of the first opening by performing an etch back of the barrier metal film in the first opening; and

embedding the first gate electrode into the first opening.

34. The method for manufacturing the semiconductor device according to claim 33,

wherein, in the step of forming the first wiring layer, a plurality of the first wirings are formed,

wherein, in the step of forming the first opening, the first opening is formed over the wiring and a second opening located over the second wiring is formed in the diffusion prevention film,

wherein, in the step of embedding the barrier metal film into the first opening, the barrier metal film is embedded also into the second opening,

the method comprising, after the step of embedding the first gate electrode into the first opening, the steps of:

allowing, an upper surface of the barrier metal film in the second opening to be located lower than an upper end of the second opening by performing an etch back of the barrier metal film in the second opening;

embedding a second gate electrode into the second opening; and

forming a second gate insulating film and a second semiconductor layer over the second gate electrode.

35. The method for manufacturing the semiconductor device according to claim 33,

wherein, in the step of forming the first wiring layer, a plurality of the first wirings are formed,

wherein, in the step of forming the first opening, the first opening is formed over the wiring and a second opening located over the second wiring is formed in the diffusion prevention film,

wherein, in the step of embedding the barrier metal film into the first opening, the barrier metal film is embedded also into the second opening,

wherein, in the step of allowing the upper surface of the barrier metal film to be located lower than the upper end of the first opening, by performing an etch back of the barrier metal film in the second opening also, the upper surface of the barrier metal film in the second opening is also located lower than the upper end of the second opening, and

wherein, in the step of embedding the first gate electrode into the first opening, the same material as that of the first gate electrode is embedded into the second opening,

the method comprising, after the step of embedding the first gate electrode into the first opening, the steps of:

removing the same material as that of the first gate electrode in the second opening;

embedding a second gate electrode into the second opening; and

forming a second gate insulating film and a second semiconductor layer over the second gate electrode.

36. The method for manufacturing the semiconductor device according to claim 30, comprising, between the step of forming the diffusion prevention film and the step of forming the opening, a step of:

forming a protective insulating film over the diffusion prevention film,

wherein, in the step of forming the opening, the opening is formed in the diffusion prevention film and the protective insulating film.