CROSS-COUPLING OF GATE CONDUCTOR LINE AND ACTIVE REGION IN SEMICONDUCTOR DEVICES

• US 20130037864A1
• Filed: 08/10/2011
• Published: 02/14/2013
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Sardesai, Viraj Y., Wong, Robert C.
• Granted Patent: US 8,853,700 B2
• Time in Patent Office: Days
• US Class Current: 257/262
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

Cross-coupling between a gate conductor and an active region of a semiconductor substrate is provided by forming a gate dielectric layer on the semiconductor substrate and lithographically patterning the gate dielectric layer to form opening therein over a portion of the active region at which electrical contact with the gate conductor is desired. After implanting electrical dopants, a gate conductor layer is deposited and patterned. A remaining portion of the gate conductor layer includes an integral conductor structure, which includes a first portion overlying a gate dielectric over an active region and a second portion contacting the semiconductor material of the same active region or a different active region. The gate dielectric layer can be deposited within gate cavities in planarization dielectric material layer in a replacement gate scheme, or can be deposited on planar surfaces of active regions and/or shallow trench isolation structures in a gate first processing scheme.

Claims

1. A semiconductor structure comprising:

a gate dielectric contacting a portion of an active region comprising a semiconductor material and located in a substrate; and

a gate conductor of unitary construction comprising a first gate conductor portion that overlies said gate dielectric and a second gate conductor portion that contacts a semiconductor surface, wherein said semiconductor surface is selected from a surface of said active region and a surface of another active region located in said substrate.

2. The semiconductor structure of claim 1, wherein said gate dielectric includes a horizontal portion and a vertical portion, said horizontal portion having a bottom surface that contacts said portion of said active region, and said vertical portion extends above a top surface of said horizontal portion.

3. The semiconductor structure of claim 2, wherein an outer sidewall of said vertical portion and a sidewall of said gate conductor are within a same vertical plane.

4. The semiconductor structure of claim 1, wherein said semiconductor surface is said surface of said another active region, and said gate dielectric contacts a top surface of a shallow trench isolation structure that laterally contacts said active region and said another active region.

5. The semiconductor structure of claim 1, wherein said gate dielectric comprises a dielectric material including at least one metal and oxygen, and has a dielectric constant greater than 8.0.

6. The semiconductor structure of claim 5, wherein said gate conductor comprises a metallic material that contacts said gate dielectric

7. The semiconductor structure of claim 1, wherein said gate dielectric includes a dielectric material that is a compound of said semiconductor material and at least one of oxygen and nitrogen.

8. The semiconductor structure of claim 1, wherein said semiconductor surface is said surface of said another active region, and said gate conductor contacts a top surface of a shallow trench isolation structure that laterally contacts said active region and said another active region.

9. The semiconductor structure of claim 1, wherein said semiconductor structure comprises a static random access memory (SRAM) cell, said second gate conductor portion contacts said surface of said another active region, said active region is a drain region of an n-type field effect transistor in said SRAM cell, and said another active region is a drain region of a p-type field effect transistor in said SRAM cell.

10. The semiconductor structure of claim 9, further comprising:

another gate dielectric contacting a portion of a drain of another n-type field effect transistor in said SRAM cell; and

another gate conductor of unitary construction overlying said another gate dielectric and contacting a drain of another p-type field effect transistor in said SRAM cell.

11. A method of forming a semiconductor structure comprising:

forming a gate cavity by removing a disposable gate structure selective to a planarization dielectric layer on a semiconductor substrate, wherein at least one surface of at least one active region is exposed within said gate cavity;

depositing a gate dielectric layer within said gate cavity;

removing a portion of said gate dielectric layer within said gate cavity from above one of said at least one active region and implanting electrical dopant into an area of said semiconductor substrate from which a portion of the said gate dielectric layer is removed; and

filling said gate cavity with a conductive material and planarizing said conductive material, wherein a gate conductor contacting a gate dielectric, which is a remaining portion of said gate dielectric layer, and a semiconductor surface of said one of said at least one active region fills said gate cavity.

12. The method of claim 11, wherein said at least one active region includes a first active region and a second active region that are laterally spaced by a shallow trench isolation structure, wherein said gate conductor is vertically spaced from said first active region by said gate dielectric and said semiconductor surface is a surface of said second active region.

13. The method of claim 11, wherein said portion of said gate dielectric layer is removed by:

applying and lithographically patterning a photoresist over said gate dielectric layer; and

etching exposed portions of said gate dielectric layer, wherein a portion of said gate dielectric layer within said gate cavity is exposed to etchants and another portion of said gate dielectric layer within said gate cavity is covered by said photoresist.

14. The method of claim 11, wherein said disposable gate structure is formed on said semiconductor substrate before depositing said planarization dielectric layer, and a top surface of said planarization dielectric layer is planarized before forming said gate cavity.

15. The method of claim 11, wherein said at least one active region includes a first active region and a second active region, and said removed portion of said gate dielectric layer overlies a portion of said second active region and does not overlie any portion of said first active region.

16. The method of claim 11, wherein said semiconductor structure comprises a static random access memory (SRAM) cell, and an end portion of said gate conductor contacts a drain region of a field effect transistor.

17. A method of forming a semiconductor structure comprising:

forming a gate dielectric layer over at least one active region in a semiconductor substrate;

removing a portion of said gate dielectric layer from above one of said at least one active region and implanting electrical dopant into an area of said semiconductor substrate from which a portion of the said gate dielectric layer is removed; and

depositing and patterning a conductive material layer to form a gate conductor, wherein said gate conductor contacts a gate dielectric, which is a remaining portion of said gate dielectric layer, and a semiconductor surface of said one of said at least one active region.

18. The method of claim 17, wherein said at least one active region includes a first active region and a second active region that are laterally spaced by a shallow trench isolation structure, wherein said gate conductor is vertically spaced from said first active region by said gate dielectric and said semiconductor surface is a surface of said second active region.

19. The method of claim 17, wherein said gate dielectric layer is deposited on all top surfaces of said at least one active region and shallow trench isolation structures.

20. The method of claim 17, wherein said semiconductor structure comprises a static random access memory (SRAM) cell, and an end portion of said gate conductor contacts a drain region of a field effect transistor.