TRENCH-GATE METAL OXIDE SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

• US 20130037880A1
• Filed: 08/09/2011
• Published: 02/14/2013
• Est. Priority Date: 08/09/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: LIU, Kuan-Ling, UENG, Shih-Yuan
• Granted Patent: US 8,643,097 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]

Abstract

A trench-gate metal oxide semiconductor device includes a substrate, a first gate dielectric layer, a first gate electrode and a first source/drain structure. The substrate has a first doping region, a second doping region and at least one trench. A P/N junction is formed between the first doping region and the second doping region. The trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction. The first gate dielectric layer is formed on a sidewall of the second trench. The first gate electrode is disposed within the trench. A height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å. The first source/drain structure is formed in the substrate and adjacent to the first gate dielectric layer.

Claims

1. A trench-gate metal oxide semiconductor device, comprising:

a substrate having a first doping region, a second doping region and at least one trench, wherein a P/N junction is formed between the first doping region and the second doping region, and the trench extends from a surface of the substrate to the first doping region through the second doping region and the P/N junction;

a first gate dielectric layer formed on a sidewall of the second trench;

a first gate electrode disposed within the trench and having a top surface, wherein a height difference between the top surface of the first gate electrode and the surface of the substrate is substantially smaller than 1500 Å

; and

a first source/drain structure formed in the substrate and adjacent to the first gate dielectric layer.

2. The trench-gate metal oxide semiconductor device according to claim 1, further comprising a dielectric capping layer for covering the top surface of the first gate electrode.

3. The trench-gate metal oxide semiconductor device according to claim 1, wherein the first doping region is an N-type well region extending from the surface of the substrate into the substrate, and the second doping region is a P-type well region extending from the surface of the substrate to the N-type well region.

4. The trench-gate metal oxide semiconductor device according to claim 3, wherein the substrate further comprises:

an N-type buried layer; and

a P-type epitaxial layer formed over the buried layer, wherein the N-type well region extends from the surface of the substrate to the P-type epitaxial layer.

5. The trench-gate metal oxide semiconductor device according to claim 3, wherein the first source/drain structure is an N-type doping structure extending from the surface of the substrate to the P-type well region along the sidewall of the trench.

6. The trench-gate metal oxide semiconductor device according to claim 1, further comprising:

a third doping region formed in the substrate and separated from the first doping region, wherein the third doping region and the first doping region have the same polarity;

a second gate dielectric layer formed on the surface of the substrate corresponding to the third doping region;

a second gate electrode formed on the second gate dielectric layer; and

a second source/drain structure formed in the third doping region and adjacent to the second gate dielectric layer, wherein the second source/drain structure and the second doping region have the same polarity.

7. A fabricating method of a trench-gate metal oxide semiconductor device, the fabricating method comprising steps of:

defining a first zone and a second zone in a substrate;

forming at least one first trench in the second zone;

forming a dielectric layer on the first zone and the second zone, and filling the dielectric layer in the first trench;

performing an etching process to form at least one second trench in the first zone by using the dielectric layer as an etching mask;

forming a first gate dielectric layer on a sidewall of the second trench; and

filling a conducting material layer into the second trench, thereby forming a first gate electrode.

8. The fabricating method according to claim 7, wherein before or after the step of forming the second trench, the fabricating method further comprises a step of forming a first source/drain structure in the first zone.

9. The fabricating method according to claim 7, wherein the dielectric layer is formed by a chemical vapor deposition process, and the conducting material layer is made of poly-silicon.

10. The fabricating method according to claim 7, wherein after the step of filling the conducting material layer, the fabricating method further comprises steps of:

forming a flat layer to cover the conducting material layer;

performing a chemical mechanical polishing process to remove the flat layer and a portion of the conducting material layer; and

performing a blanket etching process to remove the conducting material layer and the dielectric layer overlying the first zone and the second zone.

11. The fabricating method according to claim 10, wherein after the conducting material layer and the dielectric layer overlying the first zone and the second zone are removed, the fabricating method further comprises steps of:

forming a second gate dielectric layer over the second zone;

forming a second gate electrode on the second gate dielectric layer; and

forming a second source/drain structure in the second zone.

12. The fabricating method according to claim 11, wherein before the step of forming the second source/drain structure, the fabricating method further comprises a step of covering a dielectric capping layer on the first gate electrode.

13. A fabricating method of a trench-gate metal oxide semiconductor device, the fabricating method comprising steps of:

defining a first zone and a second zone in a substrate;

forming a patterned hard mask layer over the first zone and the second zone;

performing an etching process to form at least one trench in the first zone by using the patterned hard mask layer as an etch mask;

forming a first gate dielectric layer on a sidewall of the trench; and

filling a conducting material layer into the trench, thereby forming a first gate electrode.

14. The fabricating method according to claim 13, wherein before the step of forming the patterned hard mask layer, the fabricating method further comprises steps of forming at least one isolation structure in the second zone.

15. The fabricating method according to claim 14, wherein the isolation structure is a shallow trench isolation layer and the conducting material layer is made of poly-silicon.

16. The fabricating method according to claim 13, wherein the patterned hard mask layer is a multi-layered structure including a silicon oxide thin film layer and a silicon nitride thick film layer, or the patterned hard mask layer is a multi-layered structure including a silicon oxide thick film layer and a silicon nitride thin film layer.

17. The fabricating method according to claim 13, wherein after the step of filling the conducting material layer, the fabricating method further comprises steps of:

forming a flat layer to cover the conducting material layer;

performing a chemical mechanical polishing process to remove the flat layer and a portion of the conducting material layer; and

performing a blanket etching process to remove the conducting material layer and the patterned hard mask layer overlying the first zone and the second zone.

18. The fabricating method according to claim 17, wherein after the conducting material layer and the patterned hard mask layer overlying the first zone and the second zone are removed, the fabricating method further comprises steps of:

forming a second gate dielectric layer over the second zone;

forming a second gate electrode on the second gate dielectric layer; and

forming a second source/drain structure in the second zone.

19. The fabricating method according to claim 18, wherein before the step of forming the second source/drain structure, the fabricating method further comprises a step of covering a dielectric capping layer on the first gate electrode.