SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME

• US 20130037886A1
• Filed: 08/10/2011
• Published: 02/14/2013
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Tsai, Teng-Chun, Wu, Chun-Yuan, Liu, Chih-Chien, Chien, Chin-Cheng, Lin, Chin-Fu
• Granted Patent: US 9,184,100 B2
• Time in Patent Office: Days
• US Class Current: 257/351
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor substrate comprising a first active region and a second active region;

forming at least a first fin structure in the first active region, wherein the overall first fin structure has a first stress; and

forming at least a second fin structure in the second active region, wherein the overall second fin structure has a second stress different from the first stress.

2. The method for forming a semiconductor device according to claim 1, further comprising:

forming a first gate partially overlapping the first fin structure;

forming a second gate partially overlapping the second fin structure;

forming a first source/drain region in the first fin structure at two sides of the first gate; and

forming a second source/drain region in the second fin structure at two sides of the second gate.

3. The method for forming a semiconductor device according to claim 1, wherein each of the fin structures comprises a silicon-germanium-carbon material denoted as (Si_(1-x-y)Ge_xC_y), wherein x and y are zero or a positive number between 0 and 1 respectively.

4. The method for forming a semiconductor device according to claim 3, wherein the first active region comprises an n-type metal oxide semiconductor transistor (NMOS) region, and the material of the overall first fin structure comprises a ratio of y to x larger than 0.1.

5. The method for forming a semiconductor device according to claim 3, wherein the second active region comprises a p-type metal oxide semiconductor transistor (PMOS) region, and the material of the overall second fin structure comprises a ratio of y to x smaller than 0.1.

6. The method for forming a semiconductor device according to claim 1, wherein the method of forming the fin structures comprises:

forming a semiconductor layer on the semiconductor substrate;

performing an ion implantation process; and

patterning the semiconductor layer for forming the fin structures.

7. The method for forming a semiconductor device according to claim 6, wherein the semiconductor layer comprises the first stress, and the ion implantation process is performed in the second active region to form the second stress of the second fin structure.

8. The method for forming a semiconductor device according to claim 6, wherein the ion implantation process is performed in the first active region to form the first stress of the first fin structure, and another ion implantation process is further performed in the second active region to form the second stress of the second fin structure.

9. The method for forming a semiconductor device according to claim 6, wherein the ion implantation process is performed after patterning the semiconductor layer.

10. The method for forming a semiconductor device according to claim 6, wherein the semiconductor layer comprises silicon, silicon-germanium-carbon (Si_(1-x-y)Ge_xC_y), silicon-carbon (Si_(1-y)C_y) or silicon-germanium (Si_(1-x)Ge_x), wherein x and y are zero or a positive number between 0 and 1 respectively.

11. The method for forming a semiconductor device according to claim 1, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

12. The method for forming a semiconductor device according to claim 2, wherein at least one of the first gate and the second gate comprises a metal gate.

13. A semiconductor device, comprising:

a semiconductor substrate comprising at least a first active region and at least a second active region;

at least a first fin structure disposed in the first active region, wherein the overall first fin structure has a first stress; and

at least a second fin structure disposed in the second active region, wherein the overall second fin structure has a second stress different from the first stress.

14. The semiconductor device according to claim 13, further comprising:

a first gate partially overlapping the first fin structure;

a second gate partially overlapping the second fin structure;

a first source/drain region disposed in the first fin structure at two sides of the first gate; and

a second source/drain region disposed in the second fin structure at two sides of the second gate.

15. The semiconductor device according to claim 13, wherein the semiconductor substrate comprises a silicon-on-insulator (SOI) substrate or a bulk silicon substrate.

16. The semiconductor device according to claim 13, wherein the first fin structure and the second fin structure comprises a silicon-germanium-carbon semiconductor material denoted as (Si_(1-x-y)Ge_xC_y), wherein x and y are zero or a positive number between 0 and 1 respectively.

17. The semiconductor device according to claim 16, wherein the first active region comprises an n-type metal oxide semiconductor transistor (NMOS) region, and the material of the overall first fin structure comprises a ratio of y to x larger than 0.1.

18. The semiconductor device according to claim 16, wherein the second active region comprises a p-type metal oxide semiconductor transistor (PMOS) region, and the material of the overall second fin structure comprises a ratio of y to x smaller than 0.1.

19. The semiconductor device according to claim 14, wherein one of the first gate and the second gate comprises a high-k gate dielectric layer, a work function tuning layer and a metal conductive layer.

20. The semiconductor device according to claim 14, wherein at least one of the first gate and the second gate comprises a metal gate.