Multi-Chip Wafer Level Package
First Claim
1. A device comprising:
- a first semiconductor die embedded in a first photo-sensitive material layer;
a second semiconductor die stacked on top of the first semiconductor die, wherein the second semiconductor die is face-to-face coupled to the first semiconductor die;
a second photo-sensitive material layer formed on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer; and
a plurality of through vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
1 Assignment
0 Petitions
Accused Products
Abstract
A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.
-
Citations
20 Claims
-
1. A device comprising:
-
a first semiconductor die embedded in a first photo-sensitive material layer; a second semiconductor die stacked on top of the first semiconductor die, wherein the second semiconductor die is face-to-face coupled to the first semiconductor die; a second photo-sensitive material layer formed on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer; and a plurality of through vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A device comprising:
-
a first semiconductor layer comprising; a first semiconductor die embedded in a first photo-sensitive material layer; and a plurality of through vias formed in the first photo-sensitive material layer; a second semiconductor layer comprising; a second semiconductor die and a third semiconductor die are stacked together back to back through an adhesive material layer; a second photo-sensitive material layer, wherein the second semiconductor die and the third semiconductor die are embedded in the second photo-sensitive material layer; a plurality of through vias formed on top of the third semiconductor die; a third semiconductor layer having an identical structure as the second semiconductor layer; a first group of metal bumps formed between the first semiconductor layer and the second semiconductor layer; and a second group of metal bumps formed between the second semiconductor layer and the third semiconductor layer. - View Dependent Claims (10, 11, 12, 13)
-
-
14. A method comprising:
-
forming a reconfigured wafer by embedding a first semiconductor die into a first photo-sensitive material layer; forming a first group of through vias in the first photo-sensitive material layer; connecting a second semiconductor die with the first semiconductor die through a plurality of metal bumps; back-to-back attaching a third semiconductor die to the second semiconductor die using a first adhesive layer; forming a second photo-sensitive material layer containing the second semiconductor die and the third semiconductor die; and forming a second group of through vias in the second photo-sensitive material layer. - View Dependent Claims (15, 16, 17, 18, 19, 20)
-
Specification