Multi-Chip Wafer Level Package

• US 20130037950A1
• Filed: 08/10/2011
• Published: 02/14/2013
• Est. Priority Date: 08/10/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chun Hui, Tung, Chih-Hang, Shao, Tung-Liang, Yu, Chen-Hua, Shih, Da-Yuan
• Granted Patent: US 8,754,514 B2
• Time in Patent Office: Days
• US Class Current: 257/738
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/76805 the opening being a via or contact hole penetrating the underlying conductor
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/83005 being a temporary or sacrificial substrate
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06548 Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3121 : a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

Claims

1. A device comprising:

a first semiconductor die embedded in a first photo-sensitive material layer;

a second semiconductor die stacked on top of the first semiconductor die, wherein the second semiconductor die is face-to-face coupled to the first semiconductor die;

a second photo-sensitive material layer formed on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer; and

a plurality of through vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

2. The device of claim 1, further comprising:

a third semiconductor die placed on the second semiconductor die, wherein a backside of the third semiconductor die is attached to a backside of the second semiconductor die through a first adhesive material layer, wherein the third semiconductor die is embedded in the second photo-sensitive material layer.

3. The device of claim 2, wherein the plurality of through vias comprise:

a first group of through vias formed between a front side of the third semiconductor die and a top side of the second photo-sensitive material layer;

a second group of through vias formed between a front side of the first semiconductor die and a top side of the first photo-sensitive material layer; and

a third group of through vias formed through the second photo-sensitive material layer.

4. The device of claim 2, further comprising:

a base plane attached to a backside of the first semiconductor die through a second adhesive material layer;

a plurality of metal bumps formed between the first semiconductor die and the second semiconductor die;

a first redistribution layer formed on top of the first photo-sensitive material layer;

a second redistribution layer formed on top of the second photo-sensitive material layer;

an underfill material layer formed between the second semiconductor die and the first redistribution layer; and

a plurality of solder balls formed on top of the second redistribution layer.

5. The device of claim 4, wherein the first redistribution layer and the plurality of metal bumps are configured such that:

a variety of active circuits in the first semiconductor die are coupled to a variety of active circuits in the second semiconductor die through connection paths formed by the first redistribution layer and the plurality of metal bumps.

6. The device of claim 4, wherein the first redistribution layer, the plurality of metal bumps, the plurality of through vias and the second redistribution layer are configured such that:

a variety of active circuits in the first semiconductor die and a variety of active circuits in the second semiconductor die are coupled to the plurality of solder balls through connection paths formed by the first redistribution layer, the plurality of metal bumps, the plurality of through vias and the second redistribution layer.

7. The device of claim 4, wherein the plurality of through vias and the second redistribution layer are configured such that:

a variety of active circuits in the third semiconductor die are coupled to the plurality of solder balls through connection paths formed by the plurality of through vias and the second redistribution layer.

8. The device of claim 1, wherein a horizontal length of the first semiconductor die is smaller than a horizontal length of the second semiconductor die.

9. A device comprising:

a first semiconductor layer comprising;

a first semiconductor die embedded in a first photo-sensitive material layer; and

a plurality of through vias formed in the first photo-sensitive material layer;

a second semiconductor layer comprising;

a second semiconductor die and a third semiconductor die are stacked together back to back through an adhesive material layer;

a second photo-sensitive material layer, wherein the second semiconductor die and the third semiconductor die are embedded in the second photo-sensitive material layer;

a plurality of through vias formed on top of the third semiconductor die;

a third semiconductor layer having an identical structure as the second semiconductor layer;

a first group of metal bumps formed between the first semiconductor layer and the second semiconductor layer; and

a second group of metal bumps formed between the second semiconductor layer and the third semiconductor layer.

10. The device of claim 9, further comprising a first group of solder balls formed on top of the third semiconductor layer, wherein the first group of solder balls is used as input/output pads of the device.

11. The device of claim 10, wherein the first group of metal bumps and a plurality of through vias formed in the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are configured such that:

a variety of active circuits in the first semiconductor die are coupled to the first group of solder balls through connection paths formed by the first group of metal bumps and the plurality of through vias.

12. The device of claim 9, further comprising a second group of solder balls formed on a backside of the first semiconductor layer, wherein the second group of solder balls is used as input/output pads of the device.

13. The device of claim 12, wherein the first group of metal bumps and a plurality of through vias formed in the first semiconductor layer are configured such that:

a variety of active circuits in the first semiconductor die are coupled to the second group of solder balls through connection paths formed by the first group of metal bumps and the plurality of through vias.

14. A method comprising:

forming a reconfigured wafer by embedding a first semiconductor die into a first photo-sensitive material layer;

forming a first group of through vias in the first photo-sensitive material layer;

connecting a second semiconductor die with the first semiconductor die through a plurality of metal bumps;

back-to-back attaching a third semiconductor die to the second semiconductor die using a first adhesive layer;

forming a second photo-sensitive material layer containing the second semiconductor die and the third semiconductor die; and

forming a second group of through vias in the second photo-sensitive material layer.

15. The method of claim 14, further comprising:

attaching the first semiconductor die on a base plane using an adhesive layer; and

detaching the base plane from the first semiconductor die.

16. The method of claim 14, further comprising:

forming a plurality of metal bumps formed between the first semiconductor die and the second semiconductor die;

forming a first redistribution layer on top of the first photo-sensitive material layer;

forming a second redistribution layer on top of the second photo-sensitive material layer;

forming an underfill material layer between the second semiconductor die and the first redistribution layer; and

forming a plurality of solder balls on top of the second redistribution layer.

17. The method of claim 14, further comprising:

forming a second group of solder balls on a backside of the first photo-sensitive material layer.

18. The method of claim 14, further comprising:

forming a first group of openings between a front side of the third semiconductor die and a front side of the second photo-sensitive material layer;

forming a second group of openings between a front side of the first semiconductor die and a front side of the first photo-sensitive material layer; and

forming a third group of openings through the second photo-sensitive material layer.

19. The method of claim 18, further comprising:

electroplating conductive materials in the first group of openings;

electroplating conductive materials in the second group of openings; and

electroplating conductive materials in the third group of openings

20. The method of claim 14, further comprising:

sawing the reconfigured wafer into a plurality of packages, wherein each package comprises a plurality of semiconductor dies.