IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK

• US 20130038380A1
• Filed: 08/11/2011
• Published: 02/14/2013
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cordero, Edgar R., Tremaine, Robert B., Kumar, Divya, Saetow, Anuwat
• Granted Patent: US 8,692,561 B2
• Time in Patent Office: Days
• US Class Current: 327/524
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Abstract

A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.

Claims

1. A circuit for implementing a chip to chip calibration with through silicon vias (TSV) stack comprising:

a first chip;

a second chip and said first chip in a vertical semiconductor chip stack of the semiconductor chips;

at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit;

at least one of the first chip and the second chip being trained and calibrated to provide enhanced performance and reliability of the semiconductor chip stack.

2. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes at least one of the first chip and the second chip having calibration logic with control of a coupling signal for at least one of the chips in the semiconductor chip stack.

3. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes at least one of the first chip and the second chip having calibration logic for measuring a clock of another chip and adjusting a clock of at least one of the first chip and the second chip.

4. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes each of the first chip and the second chip having performance indicators and a voltage control for selectively raising or lowering a voltage of one of the chips in the semiconductor chip stack.

5. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes each of the first chip and the second chip having performance indicators and at least one of the first chip and the second chip having calibration logic.

6. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes sparing logic used to identify and replace faulty signals from each respective chip to chip interface.

7. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes delay offsets providing said calibration capability.

8. The circuit as recited in claim 1 includes a dynamic random access memory (DRAM) module, and at least one of a DRAM master chip and a DRAM slave chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit to compensate for variation in connecting paths between the DRAM master chip and DRAM slave chip.

9. The circuit as recited in claim 1 wherein at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes said performance indicator circuit selectively measuring at least one of critical path monitor, temperature, signal alignment, and dynamic random access memory (DRAM) access latency.

10. The circuit as recited in claim 1 wherein vertical semiconductor chip stack includes a through silicon vias (TSV) stack.

11. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:

a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing a chip to chip calibration, said circuit comprising;

a first chip;

a second chip and said first chip in a vertical semiconductor chip stack of the semiconductor chips;

at least one of the first chip and the second chip includes a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit;

at least one of the first chip and the second chip being trained and calibrated to provide enhanced performance and reliability of the semiconductor chip stack wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit.

12. The design structure of claim 11, wherein the design structure comprises a netlist, which describes said circuit, and wherein the design structure resides on storage medium as a data format used for the exchange of layout data of integrated circuits, and wherein the design structure includes at least one of test data files, characterization data, verification data, or design specifications.

13. The design structure of claim 11, wherein said circuit includes a dynamic random access memory (DRAM) module, and each of a DRAM master chip and DRAM slave chip including a calibration control circuit to compensate for variation in connecting paths between the DRAM master chip and DRAM slave chip.

14. The design structure of claim 11 includes each respective chip to chip interface being periodically calibrated during normal operation.

15. A method for implementing a chip to chip calibration including a first chip and a second chip in a semiconductor chip stack, said method comprising:

providing a vertical stack of the semiconductor chip stack of the semiconductor chips;

providing at least one of the first chip and the second chip with a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit; and

training and calibrating at least one of the first chip and the second chip to provide enhanced performance and reliability of the semiconductor chip stack.

16. The method as recited in claim 15 wherein providing at least one of the first chip and the second chip with a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes providing calibration logic to compensate for variation in connecting paths between the first chip and the second chip.

17. The method as recited in claim 15 wherein providing at least one of the first chip and the second chip with a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes providing calibration logic to sensing performance indicators, and selectively raises or lowers a voltage control of one of the chips in the semiconductor chip stack.

18. The method as recited in claim 15 wherein providing at least one of the first chip and the second chip with calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit includes providing calibration logic sensing performance indicators and performing calibration delay offsets.

19. The method as recited in claim 15 includes sensing performance indicators and performing calibration on power up or initialization, or on a self-timed refresh or power down state.

20. The method as recited in claim 15 wherein providing at least one of the first chip and the second chip with calibration capability includes providing sparing logic used to identify and replace faulty signals from the respective chip to chip interface.