IIMPLEMENTING CHIP TO CHIP CALIBRATION WITHIN A TSV STACK
First Claim
1. A circuit for implementing a chip to chip calibration with through silicon vias (TSV) stack comprising:
- a first chip;
a second chip and said first chip in a vertical semiconductor chip stack of the semiconductor chips;
at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit;
at least one of the first chip and the second chip being trained and calibrated to provide enhanced performance and reliability of the semiconductor chip stack.
1 Assignment
0 Petitions
Accused Products
Abstract
A method and circuit for implementing a chip to chip calibration in a chip stack, for example, with through silicon vias (TSV) stack, and a design structure on which the subject circuit resides are provided. A first chip and a second chip are included within a semiconductor chip stack. The semiconductor chip stack includes a vertical stack optionally provided with Though Silicon Via (TSV) stacking of the chips. At least one of the first chip and the second chip includes a calibration control circuit and a performance indicator circuit coupled to the calibration control circuit to train and calibrate at least one of the first chip and the second chip to provide enhanced performance and reliability for the semiconductor chip stack.
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Citations
20 Claims
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1. A circuit for implementing a chip to chip calibration with through silicon vias (TSV) stack comprising:
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a first chip; a second chip and said first chip in a vertical semiconductor chip stack of the semiconductor chips; at least one of the first chip and the second chip including a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit; at least one of the first chip and the second chip being trained and calibrated to provide enhanced performance and reliability of the semiconductor chip stack. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A design structure embodied in a machine readable medium used in a design process, the design structure comprising:
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a circuit tangibly embodied in the machine readable medium used in the design process, said circuit for implementing a chip to chip calibration, said circuit comprising; a first chip; a second chip and said first chip in a vertical semiconductor chip stack of the semiconductor chips; at least one of the first chip and the second chip includes a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit; at least one of the first chip and the second chip being trained and calibrated to provide enhanced performance and reliability of the semiconductor chip stack wherein the design structure, when read and used in the manufacture of a semiconductor chip produces a chip comprising said circuit. - View Dependent Claims (12, 13, 14)
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15. A method for implementing a chip to chip calibration including a first chip and a second chip in a semiconductor chip stack, said method comprising:
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providing a vertical stack of the semiconductor chip stack of the semiconductor chips; providing at least one of the first chip and the second chip with a calibration control circuit, and a performance indicator circuit coupled to said calibration control circuit; and training and calibrating at least one of the first chip and the second chip to provide enhanced performance and reliability of the semiconductor chip stack. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification