NON-VOLATILE STATIC RANDOM ACCESS MEMORY DEVICES AND METHODS OF OPERATIONS

• US 20130039127A1
• Filed: 08/09/2011
• Published: 02/14/2013
• Est. Priority Date: 08/09/2011
• Status: Active Grant

• Current Assignee: Synerger Incorporated
• Original Assignee: Flash Silicon Incorporation
• Inventors: WANG, Lee
• Granted Patent: US 9,779,814 B2
• Time in Patent Office: Days
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Claims

1. A non-volatile SRAM cell, comprising:

an SRAM element comprising;

a latch having two output nodes; and

two access transistors, each being coupled between one of the two output nodes and one of a bit line pair; and

a nonvolatile memory element being coupled between a voltage line and one of the two output nodes.

2. The non-volatile SRAM cell according to claim 1, wherein two gates of the two access transistors are coupled to a word line.

3. The non-volatile SRAM cell according to claim 1, wherein the latch comprises two cross-coupled inverters.

4. The non-volatile SRAM cell according to claim 1, wherein the SRAM element is a six-transistor SRAM element or a two-resistor-four-transistor SRAM element.

5. The non-volatile SRAM cell according to claim 1, wherein in an SRAM read mode and an SRAM write mode, the nonvolatile memory element is isolated from the SRAM element by turning off the nonvolatile memory element.

6. The non-volatile SRAM cell according to claim 1, which acts like an SRAM element when the nonvolatile memory element is turned off.

7. A method of transferring data between a non-volatile SRAM cell and a bit line pair, the non-volatile SRAM cell comprising an SRAM element and a non-volatile memory element, the SRAM element comprising a latch and two access transistors, the latch having two output nodes, each of the two access transistors being coupled between one of the two output nodes and one of the bit line pair, the non-volatile memory element being coupled between a voltage line and one of the two output nodes, the method comprising the steps of:

isolating the non-volatile memory element from the SRAM element by turning off the non-volatile memory element;

when the SRAM element operates in a read mode, precharging the bit line pair to a pre-determined voltage level;

when the SRAM element operates in a write mode, providing data bits on the bit line pair; and

turning on the two access transistors until one of the read mode and the write mode is completed.

8. The method according to claim 7, wherein two gates of the two access transistors are coupled to a word line.

9. The method according to claim 7, wherein the step of isolating comprises:

applying a gate voltage less than a threshold voltage of the non-volatile memory element to a control gate of the non-volatile memory element if the non-volatile memory element is N-type, otherwise applying a gate voltage greater than the threshold voltage of the non-volatile memory element to the control gate of the non-volatile memory element.

10. The method according to claim 7, wherein the pre-determined voltage level is substantially equal to an operating voltage of the SRAM element and the operating voltage is other than a ground voltage.

11. The method according to claim 7, wherein the SRAM element is a six-transistor SRAM element or a two-resistor-four-transistor SRAM element.

12. A method of loading data from a non-volatile memory element into an SRAM element in a non-volatile SRAM cell, the SRAM element comprising a latch and two access transistors, the latch having two output nodes, each of the two access transistors being coupled between one of the two output nodes and one of the bit line pair, the non-volatile memory element being coupled between a voltage line and a connecting node, the connecting node being one of the two output nodes, the method comprising:

selectively passing two data bits from the bit line pair to cause the connecting node to have a default voltage by turning on the two access transistors;

isolating the latch and the non-volatile memory element from the bit line pair by turning off the two access transistors;

applying one of a ground voltage and an operating voltage of the SRAM element to the voltage line; and

applying an intermediate voltage to a control gate of the non-volatile memory element to enable a data bit stored in the non-volatile memory element to be written to the SRAM element;

wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the non-volatile memory element.

13. The method according to claim 12, further comprising:

isolating the non-volatile memory element from the SRAM element by turning off the non-volatile memory element after the step of applying the intermediate voltage.

14. The method according to claim 12, further comprising:

selectively providing the two data bits on the bit line pair by means of an SRAM write circuit before the step of passing.

15. The method according to claim 12, wherein the step of applying one of the ground voltage and the operating voltage comprises:

applying the ground voltage to the voltage line if the non-volatile memory element is N-type, otherwise applying the operating voltage to the voltage line.

16. The method according to claim 12, wherein the default voltage is the operating voltage if the non-volatile memory element is N-type, otherwise the default voltage is the ground voltage.

17. The method according to claim 16, wherein the first threshold voltage is less than the second threshold voltage

18. The method according to claim 17, further comprising:

causing the non-volatile memory element having the first threshold voltage to be turned on to set the connecting node to the ground voltage if the non-volatile memory element is N-type, otherwise causing the non-volatile memory element having the first threshold voltage to be turned on to set the connecting node to the operating voltage after the step of applying the intermediate voltage.

19. The method according to claim 17, further comprising:

causing the non-volatile memory element having the second threshold voltage to be turned off to maintain the default voltage at the connecting node after the step of applying the intermediate voltage.

20. The method according to claim 12, wherein two gates of the two access transistors are coupled to a word line.

21. The method according to claim 12, wherein the SRAM element is a six-transistor SRAM element or a two-resistor-four-transistor SRAM element.

22. A method of storing a data bit of an SRAM element into a non-volatile memory element in a non-volatile SRAM cell, the SRAM element comprising a latch and two access transistors, the latch having two output nodes, each of the two access transistors being coupled between one of the two output nodes and one of the bit line pair, the non-volatile memory element being coupled between a voltage line and a connecting node, the connecting node being one of the two output nodes, the method comprising:

applying a first voltage to the voltage line when the non-volatile memory element has a first threshold voltage;

applying a first high voltage to the voltage line when the non-volatile memory element has a second threshold voltage;

applying a second high voltage to a control gate of the non-volatile memory element if the non-volatile memory element is N-type and has the first threshold voltage, otherwise applying a second voltage to the control gate of the non-volatile memory element; and

causing the non-volatile memory element to have a corresponding threshold voltage according to a voltage at the connecting node and a type of non-volatile memory element;

wherein the first threshold voltage is less than the second threshold voltage;

wherein the first voltage is equal to or less than a ground voltage; and

wherein the second voltage is less than an operating voltage of the SRAM element and the operating voltage is other than the ground voltage.

23. The method according to claim 22, wherein two gates of the two access transistors are coupled to a word line.

24. The method according to claim 22, wherein the SRAM element is a six-transistor SRAM element or a two-resistor-four-transistor SRAM element.

25. The method according to claim 22, wherein the first and the second high voltages are greater than the operating voltage.

26. The method according to claim 22, wherein the second voltage is close to an intrinsic threshold voltage of the non-volatile memory element if the non-volatile memory element has the second threshold voltage during the step of applying the second voltage.

27. The method according to claim 22, further comprising:

when the non-volatile memory element has the first threshold voltage, isolating the latch and the non-volatile memory element from the bit line pair by turning off the two access transistors before the step of applying the first voltage.

28. The method according to claim 22, wherein the step of causing comprises:

causing the non-volatile memory element to have the second threshold voltage if the connecting node carries the operating voltage and the non-volatile memory element is N-type; and

causing the non-volatile memory element to have the first threshold voltage if the connecting node carries the ground voltage and the non-volatile memory element is N-type,

29. The method according to claim 22, wherein the step of causing comprises:

causing the non-volatile memory element to change from a default threshold voltage if the connecting node carries the operating voltage and the non-volatile memory element is P-type; and

causing the non-volatile memory element to maintain the default threshold voltage if the connecting node carries the ground voltage and the non-volatile memory element is P-type,

30. The method according to claim 29, wherein the step of causing the non-volatile memory element to change from the default threshold voltage state further comprises:

causing the non-volatile memory element to have the second threshold voltage if the non-volatile memory element have the default threshold voltage equal to the first threshold voltage; and

causing the non-volatile memory element to have the first threshold voltage if the non-volatile memory element have the default threshold voltage equal to the second threshold voltage.