Data Storage for Voltage Domain Crossings

• US 20130039133A1
• Filed: 08/12/2011
• Published: 02/14/2013
• Est. Priority Date: 08/12/2011
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Koob, Christopher Edward, Lin, Jen Tsung, Pyla, Manojkumar, Saint-Laurent, Martin
• Granted Patent: US 8,995,207 B2
• Time in Patent Office: Days
• US Class Current: 365/189.11
• CPC Class Codes: G06F 2205/102 Avoiding metastability, i.e. preventing hazards, e.g. by using Gray code counters
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: G06F 5/10 having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory G06F5/065 takes precedence
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence

Abstract

According to an embodiment, an apparatus includes a data storage device. Data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device. The data storage device is powered by the second voltage domain. The apparatus further includes a circuit that is powered by the second voltage domain and that is responsive to data output by the data storage device.

Claims

1. An apparatus comprising:

a data storage device, wherein data to be stored in the data storage device is level shifted from a first voltage domain to a second voltage domain prior to being stored within the data storage device, and wherein the data storage device is powered by the second voltage domain; and

a circuit powered by the second voltage domain, the circuit responsive to data output by the data storage device.

2. The apparatus of claim 1, wherein the data storage device has a single data input and multiple data outputs per bit lane, and wherein the data storage device is in a first clock domain and the circuit is in a second clock domain.

3. The apparatus of claim 2, further comprising a first level shifter coupled to the single data input, and wherein the first level shifter is configured to level shift the data to be stored from a first voltage level associated with the first voltage domain to a second voltage level associated with the second voltage domain.

4. The apparatus of claim 3, further comprising:

control logic to control read and write operations at the data storage device, the control logic responsive to a clock signal, to a write enable signal, and to a write address signal;

a second level shifter configured to level shift a clock input to generate the clock signal;

a third level shifter configured to level shift a write enable input to generate the write enable signal; and

a fourth level shifter configured to level shift a write address input to generate the write address signal.

5. The apparatus of claim 4, wherein the single data input and the multiple data outputs are separated by a clock domain crossing.

6. The apparatus of claim 1, wherein the data storage device includes an asynchronous first-in first-out (FIFO) buffer.

7. The apparatus of claim 6, wherein the asynchronous FIFO buffer includes multiple latching elements.

8. The apparatus of claim 7, wherein the asynchronous FIFO buffer is coupled to provide an output that has a voltage level associated with the second voltage domain.

9. A method comprising:

level shifting a data input signal to a data storage device from a first voltage level associated with a first voltage domain to a second voltage level associated with a second voltage domain, wherein the data storage device is powered by the second voltage domain; and

sending an output of the data storage device to a circuit powered by the second voltage domain, wherein the data storage device is in a first clock domain and the circuit is in a second clock domain.

10. The method of claim 9, further comprising storing data corresponding to the data input signal at the data storage device.

11. The method of claim 10, further comprising updating a write pointer in response to storing the data.

12. The method of claim 11, further comprising generating multiple data outputs at the data storage device that correspond to the data.

13. The method of claim 9, wherein the data input signal is separated by a clock domain crossing from the multiple data outputs.

14. The method of claim 13, further comprising updating a read pointer in response to generating the multiple data outputs.

15. An apparatus comprising:

means for storing data; and

means for level shifting a data input signal to the means for storing data from a first voltage level associated with a first voltage domain to a second voltage level associated with a second voltage domain,

wherein the means for storing data is powered by the second voltage domain.

16. The apparatus of claim 15, wherein the means for level shifting includes a level shifter coupled to an input of the means for storing data.

17. The apparatus of claim 16, wherein an input of the means for level shifting is associated with the first voltage domain, and wherein an output of the means for level shifting is associated with the second voltage domain.

18. A device comprising:

a first voltage domain associated with a first voltage supply and including first circuitry powered by the first voltage supply;

a second voltage domain associated with a second voltage supply and including second circuitry powered by the second voltage supply;

a data storage device powered by the second voltage domain; and

a level shifter coupled to an input of the data storage device and configured to level shift data to be stored at the data storage device from the first voltage domain to the second domain prior to being stored within the data storage device.

19. The device of claim 18, wherein a voltage domain crossing divides the first voltage domain and the second voltage domain.

20. The device of claim 19, wherein the input of the data storage device is associated with a first clock domain, and wherein an output of the data storage device is associated with a second clock domain, and wherein a clock domain crossing divides the first clock domain and the second clock domain.

21. The device of claim 18, wherein the data storage device includes an asynchronous first-in first-out (FIFO) buffer, and wherein the asynchronous FIFO buffer is responsive to a clock signal, to a write enable signal, and to a write address signal.

22. The device of claim 21, further comprising a write counter configured to store a write counter value that points to a next storage location of the asynchronous FIFO buffer to be written to.

23. The device of claim 22, wherein the write counter is a Gray counter or a Johnson counter.

24. The device of claim 22, further comprising logic to receive the write counter value at the second voltage domain.

25. The device of claim 24, wherein the logic to receive the write counter value includes a pair of latching elements powered by the second voltage domain.

26. The device of claim 25, further comprising first equivalence check logic configured to compare the write counter value with the read counter value.

27. The device of claim 26, further comprising a read counter configured to store a read counter value that points to a next storage location of the asynchronous FIFO buffer to be read.

28. The device of claim 27, wherein the read counter is a Gray counter or a Johnson counter.

29. The device of claim 27, further comprising logic to receive the read counter value at the first voltage domain.

30. The device of claim 29, wherein the logic to receive the read counter value includes a pair of latching elements located at the first voltage domain.

31. The device of claim 30, further comprising second equivalence check logic configured to compare the write counter value with the read counter value.

32. The device of claim 29, wherein a FIFO depth signal is generated based on the write counter value and the read counter value.