SYNCHRONIZED CODE RECOGNITION
First Claim
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1. A method, comprising:
- recognizing, by a satellite controller, one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller;
generating, by a synchronous clock signal generator, a synchronous clock signal responsive to recognition by the satellite controller of the one or more synchronization codes of the plurality of synchronization codes; and
generating, by an internal clock signal generator, an internal clock signal for the satellite controller, wherein the internal clock signal is separate from the synchronous clock signal.
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Abstract
A system includes a central controller to transmit a plurality of synchronization codes through a transmission medium and a plurality of satellite controllers, each satellite controller configured to recognize one or more synchronization codes of the plurality of synchronization codes, each satellite controller comprising a synchronous clock signal generator to generate a synchronous clock signal each time the satellite controller recognizes the one or more synchronization codes of the plurality of synchronization codes.
12 Citations
20 Claims
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1. A method, comprising:
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recognizing, by a satellite controller, one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller; generating, by a synchronous clock signal generator, a synchronous clock signal responsive to recognition by the satellite controller of the one or more synchronization codes of the plurality of synchronization codes; and generating, by an internal clock signal generator, an internal clock signal for the satellite controller, wherein the internal clock signal is separate from the synchronous clock signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method, comprising:
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recognizing, by a satellite controller, one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller; generating, by a synchronous clock signal generator, a synchronous clock signal responsive to recognition by the satellite controller of the one or more synchronization codes of the plurality of synchronization codes; generating, by an internal clock signal generator, an internal clock signal for the satellite controller; triggering a programmable timer with the synchronous clock signal, wherein the programmable timer is coupled with the synchronous clock signal generator and the internal clock signal generator; clocking the programmable timer with the internal clock signal; and switching a peripheral device, using the programmable timer, between a first state and a second state. - View Dependent Claims (15, 16, 17)
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18. A system, comprising:
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a satellite controller configured to recognize one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller; a synchronous clock signal generator configured to generate a synchronous clock signal responsive to recognition by the satellite controller of the one or more synchronization codes; and an internal clock signal generator configured to generate a separate internal clock signal for the satellite controller. - View Dependent Claims (19)
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20. A system, comprising:
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a satellite controller configured to recognize one or more synchronization codes of a plurality of synchronization codes transmitted from a central controller; a synchronous clock signal generator configured to generate a synchronous clock signal responsive to recognition by the satellite controller of the one or more synchronization codes; an internal clock signal generator configured to generate an internal clock signal for the satellite controller; and a programmable timer coupled with the synchronous clock signal generator and the internal clock signal generator, wherein the programmable timer is configured to; be triggered by the synchronous clock signal; be clocked with the internal clock signal; and switch a peripheral device between a first state and a second state depending on a detected difference between the synchronous clock signal and the internal clock signal.
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Specification