Method for Manufacturing a Semiconductor Device

• US 20130040443A1
• Filed: 10/16/2012
• Published: 02/14/2013
• Est. Priority Date: 01/13/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Poelzl, Martin
• Granted Patent: US 9,806,187 B2
• Time in Patent Office: Days
• US Class Current: 438/478
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is formed on the horizontal surface. An epitaxial region is formed by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask. The epitaxial region is polished by a chemical-mechanical polishing process stopping on the epitaxy hard mask. A vertical trench is formed in the semiconductor body. An insulated field plate is formed in a lower portion of the vertical trench and an insulated gate electrode is formed above the insulated field plate. Further, a method for forming a field-effect semiconductor device is provided.

Claims

1. A method for forming a semiconductor device, comprising:

providing a semiconductor body having a horizontal surface;

forming an epitaxy hard mask on the horizontal surface;

forming an epitaxial region by selective epitaxy on the horizontal surface relative to the epitaxy hard mask so that the epitaxial region is adjusted to the epitaxy hard mask;

polishing the epitaxial region by a chemical-mechanical polishing process stopping on the epitaxy hard mask;

forming a vertical trench from the horizontal surface into the semiconductor body;

forming an insulated field plate in a lower portion of the vertical trench comprising forming a field oxide; and

forming an insulated gate electrode above the insulated field plate such that the field oxide extends, in a vertical direction, up to the epitaxial region.

2. The method of claim 1, wherein the epitaxy hard mask has a vertical extension of about 300 nm to about 600 nm.

3. The method of claim 1, wherein the semiconductor body comprises in an upper portion extending to the horizontal surface a first conductivity type, and wherein forming the epitaxial region comprises forming an epitaxial region of the first conductivity type on the semiconductor body and an epitaxial region of a second conductivity type on the epitaxial region of the first conductivity type.

4. The method of claim 1, further comprising forming a trench hard mask which is self-aligned to the epitaxial region, and wherein forming a vertical trench comprises etching into the semiconductor body through the trench hard mask.

5. The method of claim 4, further comprising removing the epitaxy hard mask selectively to the epitaxial region prior to forming the trench hard mask.

6. The method of claim 1, further comprising:

forming a trench hard mask prior to forming the epitaxy hard mask, wherein the epitaxy hard mask is formed self-aligned to the trench hard mask; and

removing the trench hard mask selectively to the epitaxy hard mask prior to forming the epitaxial region.

7. The method of claim 1, wherein the epitaxy hard mask comprises at least one of a thermal oxide layer, a TEOS layer, an undoped silicate glass layer, a high density plasma oxide layer, and a doped oxide layer.

8. A method for forming a semiconductor device, comprising:

providing a semiconductor body having a horizontal surface;

forming an epitaxy hard mask on the horizontal surface;

depositing a semiconductor material on the semiconductor body by epitaxial deposition selective to the epitaxy hard mask by selective epitaxy so that, in a vertical cross-section, at least two spaced apart epitaxial regions are formed;

removing the epitaxy hard mask selective to the semiconductor material so that, in the vertical cross-section, sidewalls of the at least two spaced apart epitaxial regions are exposed;

forming a trench hard mask comprising forming a dielectric layer so that, in the vertical cross-section, each of the sidewalls of the at least two spaced apart epitaxial regions is covered by the dielectric layer;

etching a vertical trench into the semiconductor body using the trench hard mask as an etching mask; and

forming an insulated gate electrode which is, in the vertical cross-section, arranged between the at least two spaced apart epitaxial regions.

9. The method of claim 8, further comprising polishing the semiconductor material back to the epitaxy hard mask.

10. The method of claim 8, wherein forming the epitaxy hard mask comprises at least one of:

forming a thermal oxide layer; and

depositing a nitride layer and depositing a TEOS layer.

11. The method of claim 8, further comprising forming an insulated field plate in a lower portion of the vertical trench.

12. The method of claim 8, wherein the semiconductor device comprises an active area and a peripheral area, the method further comprising:

forming a plurality of vertical trenches in the active area and at least one vertical trench in the peripheral area; and

forming insulated gate electrodes only in the active area.

13. A method for forming a field-effect semiconductor device, comprising:

providing a semiconductor body having a horizontal surface;

forming a trench hard mask on the horizontal surface and a vertical trench in the semiconductor body self-aligned to the trench hard mask;

forming an insulated field plate in a lower portion of the vertical trench;

forming an epitaxy hard mask which is self-aligned to the trench hard mask;

removing the trench hard mask selectively to the epitaxy hard mask to partly expose the semiconductor body;

depositing a semiconductor material on the semiconductor body by epitaxial deposition selective to the epitaxy hard mask by selective epitaxy so that, in a vertical cross-section, at least two spaced apart epitaxial regions are formed;

removing the epitaxy hard mask so that, in the vertical cross-section, sidewalls of the at least two spaced apart epitaxial regions are exposed; and

forming an insulated gate electrode which is, in the vertical cross-section, arranged between the at least two spaced apart epitaxial regions.

14. The method of claim 13, wherein forming the epitaxy hard mask comprises forming a dielectric plug in the vertical trench such that the dielectric plug extends beyond the horizontal surface.

15. The method of claim 14, further comprising forming an amorphous silicon layer at least between the dielectric plug and the semiconductor body.

16. The method of claim 13, wherein forming the hard mask and the vertical trench comprises depositing a nitride layer.

17. The method of claim 13, wherein forming the insulated field plate comprises:

insulating walls of the vertical trench;

depositing a conductive layer; and

back-etching the conductive region selectively to the trench hard mask.

18. The method of claim 17, further comprising at least one of:

covering the trench hard mask and an upper portion of the insulated side walls with a further nitride layer;

covering the trench hard mask and an upper portion of the insulated side walls with an amorpheous silicon layer;

depositing a TEOS layer;

depositing an undoped silicate glass layer; and

forming a flat horizontal surface above the horizontal surface by a chemical-mechanical polishing process stopping on the trench hard mask.

19. A method for forming a field-effect semiconductor device, comprising:

providing a semiconductor body having a horizontal surface and a hard mask layer on the horizontal surface;

forming a vertical trench in the hard mask layer and the semiconductor body;

forming a field oxide on a side wall and a bottom wall of the vertical trench;

forming a field plate in a lower portion of the vertical trench;

forming a liner layer covering at least the trench hard mask and an upper portion of the field oxide;

forming a dielectric plug in an upper portion of the vertical trench, the dielectric plug extending beyond the horizontal surface;

removing the trench hard mask to partly expose the semiconductor body;

depositing a semiconductor material on the semiconductor body by epitaxial deposition selective to the dielectric plug by selective epitaxy so that, in a vertical cross-section, at least two spaced apart epitaxial regions are formed;

exposing, in the vertical cross-section, sidewalls of the at least two spaced apart epitaxial regions by removing the dielectric plug at least between at least two spaced apart epitaxial regions.

20. The method of claim 19, wherein the trench hard mask comprises a stack of dielectric layers.

21. The method of claim 19, wherein the liner layer comprises an amorphous silicon layer.