SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE DEVICE

• US 20130043490A1
• Filed: 02/14/2012
• Published: 02/21/2013
• Est. Priority Date: 06/28/2011
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Sorada, Haruyuki
• Granted Patent: US 8,563,987 B2
• Time in Patent Office: Days
• US Class Current: 257/77
• CPC Class Codes: H01L 21/044 Conductor-insulator-semiconductor electrodes
• CPC Class Codes: H01L 21/049 Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
• CPC Class Codes: H01L 21/28264 the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/515 with cavities, e.g. containing a gas
• CPC Class Codes: H01L 29/66045 Field-effect transistors
• CPC Class Codes: H01L 29/66068 the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

The semiconductor device 100 of this invention includes: a semiconductor layer 2 arranged on the principal surface of a substrate 1 and made of a wide bandgap semiconductor; a trench 5 which is arranged in the semiconductor layer 2 and which has a bottom and a side surface; an insulating region 11 arranged on the bottom and side surface of the trench 5; and a conductive layer 7 arranged in the trench 5 and insulated from the semiconductor layer 2 by the insulating region 11. The insulating region 11 includes a gate insulating film 6 arranged on the bottom and the side surface of the trench 5 and a gap 10 arranged between the gate insulating film 6 and the conductive layer 7 at the bottom of the trench 5. The gate insulating film 6 contacts with the conductive layer 7 on a portion of the side surface of the trench 5 but does not contact with the conductive layer 7 at the bottom of the trench 5. The thickness of the insulating region 11 measured from the bottom of the trench 5 through the lower surface of the conductive layer 7 is greater around the center of the trench than beside its side surface.

Claims

1. A semiconductor device comprising:

a substrate;

a semiconductor layer which is arranged on the principal surface of the substrate and which is made of a wide bandgap semiconductor;

a trench which is arranged in the semiconductor layer and which has a bottom and a side surface;

an insulating region which is arranged on the bottom and side surface of the trench; and

a conductive layer which is arranged in the trench and which is insulated from the semiconductor layer by the insulating region,

wherein the insulating region includes a gate insulating film that is arranged on the bottom and the side surface of the trench and a gap that is arranged between the gate insulating film and the conductive layer at the bottom of the trench, and

wherein the gate insulating film contacts with the conductive layer on a portion of the side surface of the trench but does not contact with the conductive layer at the bottom of the trench, and

wherein the thickness of the insulating region as measured from the bottom of the trench through the lower surface of the conductive layer is greater around the center of the trench than beside the side surface of the trench.

2. The semiconductor device of claim 1, wherein the semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type which is arranged on the drift region, and a doped region of the first conductivity type which is arranged on the body region, and

wherein the trench runs through the doped region and the body region and its bottom is located in the drift region, and

wherein a portion of the lower surface of the conductive layer, which is located beside the side surface of the trench, is deeper than an interface between the body region and the drift region.

3. The semiconductor device of claim 2, wherein a portion of the lower surface of the conductive layer, which is located around the center of the trench, is shallower than the interface between the body region and the drift region.

4. The semiconductor device of claim 1, wherein the gap is taller around the center of the trench than beside the side surface of the trench.

5. The semiconductor device of claim 1, wherein the bottom of the trench is deeper around the center of the trench than beside the side surface of the trench.

6. The semiconductor device of claim 1, wherein the gap is arranged at the bottom of the trench and at a corner portion that is defined by the bottom and the side surface of the trench.

7. The semiconductor device of claim 1, wherein the minimum value of the thickness of the insulating region as measured from the bottom of the trench through the lower surface of the conductive layer is five times or more as large as the thickness of the insulating region on the side surface of the trench.

8. The semiconductor device of claim 2, further comprising a second semiconductor layer of the first conductivity type, which is arranged between the body region that is exposed on the side surface of the trench and the gate insulating film.

9. The semiconductor device of claim 1, wherein the wide bandgap semiconductor is silicon carbide.

10. The semiconductor device of claim 9, wherein the gate insulating film is a silicon oxide film and wherein the gate insulating film is less thick at the bottom of the trench than on the side surface of the trench.

11. The semiconductor device of claim 1, wherein the electric field intensity is less than 4 MV/cm at the bottom of the trench.

12. A method for fabricating a semiconductor device, the method comprising the steps of:

(A) providing a substrate, on the principal surface of which a semiconductor layer of a wide bandgap semiconductor is formed;

(B) forming a trench, which has a bottom and a side surface, in the semiconductor layer;

(C) forming a gate insulating film on the bottom and side surface of the trench; and

(D) forming a conductive layer in the trench so that the conductive layer contacts with the gate insulating film on a portion of the side surface of the trench but does not contact with the gate insulating film at the bottom of the trench and that a gap is left between the conductive layer and the gate insulating film, thereby having an insulating region defined by the gap and the gate insulating film, wherein the thickness of the insulating region as measured from the bottom of the trench through the lower surface of the conductive layer is greater around the center of the trench than beside the side surface of the trench.

13. The method of claim 12, wherein in the step (A), the semiconductor layer includes a drift region of a first conductivity type, a body region of a second conductivity type which is arranged on the drift region, and a doped region of the first conductivity type which is arranged on the body region, and

wherein in the step (B), the trench is formed so that the trench runs through the doped region and the body region to have its bottom located in the drift region, and

wherein in the step (D), the conductive layer is formed so that a portion of the lower surface of the conductive layer, which is located beside the side surface of the trench, is deeper than an interface between the body region and the drift region.

14. The method of claim 12, wherein the gap is taller around the center of the trench than beside the side surface of the trench.

15. The method of claim 13, wherein the step (D) includes the step (D1) of depositing a material of the conductive layer on the side surface of the trench from a first direction which tilts with respect to a normal to the principal surface of the substrate.

16. The method of claim 15, wherein the step (D1) includes depositing the material of the conductive layer from the first direction while rotating the substrate within a plane that is parallel to the principal surface of the substrate, and

wherein the angle θ

defined between the first direction and the principal surface of the substrate is set so as to satisfy b>

a×

tan θ

>

d and b−

a×

tan θ

>

350 nm, where a is the width of the trench, b is the depth of the trench as measured from the surface of the semiconductor layer, and d is the depth of the interface between the body region and the drift region as measured from the surface of the semiconductor layer.

17. The method of claim 15, wherein the step (D1) includes depositing the material of the conductive layer from at least the first direction and a second direction that is opposed to the first direction, and

wherein the angle θ

defined between the first direction and the principal surface of the substrate is set so as to satisfy b>

a′

×

tan θ

>

d and b−

a′

×

tan θ

>

350 nm, where a′

is the width of the trench as measured on a cross section including the first direction, b is the depth of the trench as measured from the surface of the semiconductor layer, and d is the depth of the interface between the body region and the drift region as measured from the surface of the semiconductor layer.