Semiconductor Structure And Method For Manufacturing The Same

• US 20130043517A1
• Filed: 12/01/2011
• Published: 02/21/2013
• Est. Priority Date: 08/19/2011
• Status: Abandoned Application

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences
• Inventors: Yin, Haizhou, Luo, Zhijiong, Zhu, Huilong
• Application Number:
  US13/505,731
• Publication Number:
  US 20130043517A1
• Time in Patent Office: Days
• US Class Current: 257/288
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The present invention provides a method for manufacturing a semiconductor structure, which comprises: providing a substrate, and forming a dielectric layer and a dummy gate layer on the substrate; performing doping and annealing to the dummy gate layer; patterning the dummy gate layer to form a dummy gate, wherein the top cross section of the dummy gate is larger than the bottom cross section of the dummy gate; forming sidewall spacers and source/drain regions; depositing an interlayer dielectric layer and planarizing the same; removing the dummy gate to form an opening within the sidewall spacers; and forming a gate in the opening. Accordingly, the present invention further provides a semiconductor structure. The present invention proposes to form a dummy gate in the shape of a reverse taper, which is capable of alleviating processing difficulty of removing the dummy gate and filling gate material at subsequent steps, and thereby favorably avoiding occurrence of voids or the like and enhancing reliability of devices.

Claims

1. A method for manufacturing a semiconductor structure, comprising:

(a) providing a substrate, and forming a dielectric layer and a dummy gate layer on the substrate;

(b) performing doping and annealing to the dummy gate layer;

(c) patterning the dummy gate layer to form a dummy gate, wherein the top cross section of the dummy gate is larger than the bottom cross section of the dummy gate;

(d) forming sidewall spacers and source/drain regions;

(e) depositing an interlayer dielectric layer and planarizing the interlayer dielectric layer;

(f) removing the dummy gate to form an opening within the sidewall spacers; and

(g) forming a gate in the opening.

2. The method of claim 1, wherein at step (b), the doping method is diffusion or ion implantation, and the dopant ion is the ion of B, P, or As.

3. The method of claim 1, wherein at step (b), the doping concentration at the surface of the dummy gate layer is 1×

10¹⁹ cm<sup>−

3</sup> to 1×

10²¹ cm<sup>−

3</sup>; and

the annealing is performed such that the distribution of doping concentration within the dummy gate layer is gradually lower inwards from the surface of the dummy gate layer.

4. The method of claim 1, wherein at step (c), patterning the dummy gate layer to form the dummy gate comprises:

forming a hard mask layer on the dummy gate layer, wherein the hard mask layer corresponds to the shape of the top surface of the dummy gate to be formed; and

wet etching the exposed dummy gate layer using KOH, TMAH, or EDP.

5. The method of claim 4, further comprising, prior to wet etching, etching the exposed dummy gate layer through reactive ion etching.

6. The method of claim 1, wherein

step (d) further comprises forming source/drain extension regions prior to the formation of the source/drain regions;

and

step (d) further comprises forming silicide contacts on the surfaces of the source/drain regions after the formation of the source/drain regions.

7. The method of claim 6, further comprising removing the exposed dielectric layer after the formation of the dummy gate at step (c) or prior to the formation of the silicide contacts at step (d).

8. The method of claim 1, further comprising removing the dielectric layer located below the dummy gate at step (f).

9. The method of claim 1, further comprising, at step (g), forming a gate dielectric layer in the opening prior to the formation of the gate, wherein the material of the gate dielectric layer comprises at least one material selected from a group consisting of SiO₂, Si₃N₄, HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al₂O₃, La₂O₃, ZrO₂, and LaAlO.

12. The method of claim 3, wherein at step (c), patterning the dummy gate layer to form the dummy gate comprises:

forming a hard mask layer on the dummy gate layer, wherein the hard mask layer corresponds to the shape of the top surface of the dummy gate to be formed; and

wet etching the exposed dummy gate layer using KOH, TMAH, or EDP.

13. The method of claim 8, further comprising, at step (g), forming a gate dielectric layer in the opening prior to the formation of the gate, wherein the material of the gate dielectric layer comprises at least one material selected from a group consisting of SiO₂, Si₃N₄, HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al₂O₃, La₂O₃, ZrO₂, and LaAlO.

10. A semiconductor structure, which comprises a substrate, a gate stack, sidewall spacers, and source/drain regions, wherein

the gate stack is located on the substrate and comprises a gate dielectric layer and a gate, and the top cross section of the gate is larger than the bottom cross section of the gate, the gate dielectric layer being sandwiched between the gate and the substrate, or alternatively, the gate dielectric layer being covering the sidewalls and the bottom of the gate;

the sidewall spacers are located on both sides of the gate stack; and

the source/drain regions are formed within the substrate and located on opposite sides of the gate stack.

11. The semiconductor structure of claim 10, wherein the angle between the sidewalls of the gate and the substrate is in the range of 45°

to 85°

.