SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20130043537A1
• Filed: 03/09/2011
• Published: 02/21/2013
• Est. Priority Date: 03/09/2010
• Status: Active Grant

• Current Assignee: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: Inter-University Research Institute Corporation High Energy Accelerator Research Organization, LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Inventors: Okihara, Masao, Kasai, Hiroki, Arai, Yasuo
• Granted Patent: US 8,963,246 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/225 using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer H01L21/221 - H01L21/222 take precedence
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1443 with at least one potential jump or surface barrier
• CPC Class Codes: H01L 27/1461 characterised by the photosensitive area
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14658 X-ray, gamma-ray or corpuscular radiation imagers measuring X-, gamma- or corpuscular radiation G01T1/00
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes

Abstract

There is provided a semiconductor device and a method for manufacturing a semiconductor device. Within the N-type semiconductor layer formed from a high resistance N-type substrate, the P-type well diffusion layer and P-type extraction layer are formed and are fixed to ground potential. Due thereto, a depletion layer spreading on the P-type well diffusion layer side does not reach the interlayer boundary between the P-type well diffusion layer and the buried oxide film. Hence, the potential around the surface of the P-type well diffusion layer is kept at a ground potential. Accordingly, when the voltages are applied to the backside of the N-type semiconductor layer and a cathode electrode, a channel region at the MOS-type semiconductor formed as a P-type semiconductor layer is not activated. Due thereto, leakage current that may occur independently of a control due to the gate electrode of a transistor can be suppressed.

Claims

1. A semiconductor device comprising:

a second-conductive-type semiconductor layer in which, a first first-conductive-type region is formed in a predetermined first region on one surface side of the second-conductive-type semiconductor layer, a second first-conductive-type region with a higher impurity concentration than that in the first first-conductive-type region is formed in a portion of the first first-conductive-type region, and a first second-conductive-type region with a high impurity concentration and a third first-conductive-type region are formed at a portion of a second region adjacent to the first region;

an oxide film layer that is laminated on the first region and the second region on the one surface side of the second-conductive-type semiconductor layer;

a MOS-type transistor that includes a first-conductive-type semiconductor layer laminated on the oxide film layer in the first region;

a first electrode that is connected to the second first-conductive-type region;

a second electrode that is connected to the first second-conductive-type region; and

a third electrode that is connected to the third first-conductive-type region.

2. The semiconductor device according to claim 1, further comprising

a voltage applying unit for applying voltage to a surface opposite to the one surface of the second-conductive-type semiconductor layer and the second electrode,

wherein the first electrode and the third electrode are connected to ground.

3. The semiconductor device according to claim 1, wherein

a second second-conductive-type region is formed in the first first-conductive-type region so as to be in contact with the oxide film layer and, a third second-conductive-type region with a higher impurity concentration than that in the second second-conductive-type region is formed in a portion of the second-conductive-type second region,

wherein the semiconductor device comprises a fourth electrode connected to the third second-conductive-type region.

4. The semiconductor device according to claim 3, further comprising

a voltage applying unit for applying voltage to a surface opposite to the one surface of the second-conductive-type semiconductor layer and the second electrode,

wherein the first electrode, the third electrode and the fourth electrode are connected to ground.

5. A method for manufacturing a semiconductor device comprising:

laminating an oxide film layer and a first-conductive-type semiconductor layer on a second-conductive-type semiconductor layer in order;

forming an active region in the first-conductive-type semiconductor layer;

forming an insulating film on the first-conductive-type semiconductor layer;

forming a first first-conductive-type region by diffusing, based on the position of the active region, a first-conductive-type impurity within a first region of the second-conductive-type semiconductor layer that includes a lower portion of the active region;

forming a MOS-type transistor in the active region;

removing the oxide film layer from a predetermined region in which a first electrode, a second electrode and a third electrode of the second-conductive-type semiconductor layer are to be formed;

forming, in the first first-conductive-type region, a second first-conductive-type region by diffusing the first-conductive-type impurity within the predetermined region from which the oxide film layer has been removed and on which the first electrode is to be formed and, forming a third first-conductive-type region by diffusing the first-conductive-type impurity within the predetermined region on which the third electrode is to be formed;

forming a second-conductive-type region by diffusing a second-conductive-type impurity within the predetermined region from which the oxide film layer has been removed and in which the second electrode is to be formed; and

forming the first electrode, the second electrode and the third electrode.

6. The method for manufacturing the semiconductor device according to claim 5, further comprising,

forming, between the process of forming the insulating film and the process of forming the first first-conductive-type region, a second second-conductive-type region by diffusing, based on the position of the active region, the second-conductive-type impurity within a first region of the second-conductive-type semiconductor layer including a lower portion of the active region.