SEMICONDUCTOR DEVICE

• US 20130043581A1
• Filed: 08/13/2012
• Published: 02/21/2013
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Original Assignee: Shinko Electric Industries Company Limited (Fujitsu Limited)
• Inventors: Negoro, Syuji
• Granted Patent: US 8,558,372 B2
• Time in Patent Office: Days
• US Class Current: 257/712
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/3675 characterised by the shape of the housing
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15153 the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/16151 Cap comprising an aperture, e.g. for pressure control, encapsulation
• CPC Class Codes: H01L 2924/16195 Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/16251 Connecting to an item not being a semiconductor or solid-state body, e.g. cap-to-substrate

Abstract

A semiconductor device includes a wiring substrate, a first semiconductor chip mounted on the wiring substrate, and a second semiconductor chip mounted on the wiring substrate. The second semiconductor chip generates less heat than the first semiconductor chip. A heat dissipation plate is arranged on the wiring substrate and partially at a higher location than the first and second semiconductor chips. The heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip. The upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening.

Claims

1. A semiconductor device comprising:

a wiring substrate;

a first semiconductor chip mounted on the wiring substrate;

a second semiconductor chip mounted on the wiring substrate, wherein the second semiconductor chip generates less heat than the first semiconductor chip; and

a heat dissipation plate arranged on the wiring substrate and partially at a higher location than the first semiconductor chip and the second semiconductor chip, wherein

the heat dissipation plate is connected to the first semiconductor chip,

the heat dissipation plate includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip, and

the upper surface of the second semiconductor chip is entirely exposed from the heat dissipation plate through the opening.

2. The semiconductor device according to claim 1, wherein the second semiconductor chip is put in the opening, and the semiconductor device further comprises a thermal insulation resin formed between the second semiconductor chip and a wall defining the opening.

3. The semiconductor device according to claim 1, further comprising a thermal insulation resin arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.

4. The semiconductor device according to claim 2, further comprising a thermal insulation resin arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.

5. The semiconductor device according to claim 1, wherein the second semiconductor chip is free from contact with a wall defining the opening.

6. The semiconductor device according to claim 5, wherein an air passage is formed between the second semiconductor chip and the wall defining the opening.

7. The semiconductor device according to claim 5, wherein a thermal insulation resin is formed between the second semiconductor chip and the wall defining the opening.

8. The semiconductor device according to claim 1, further comprising a heat dissipation portion arranged on the heat dissipation plate and connected to the heat dissipation plate and the second semiconductor chip.

9. A semiconductor device comprising:

a wiring substrate;

a first semiconductor chip mounted on the wiring substrate;

a second semiconductor chip mounted on the wiring substrate, wherein the second semiconductor chip generates less heat than the first semiconductor chip;

a first heat dissipation plate arranged on the wiring substrate and partially at a higher location than the first semiconductor chip and the second semiconductor chip, wherein the first heat dissipation plate is connected to the first semiconductor chip and includes an opening formed at a location corresponding to an upper surface of the second semiconductor chip;

a second heat dissipation plate arranged in the opening and connected to the second semiconductor chip; and

a thermal insulation resin formed between the second heat dissipation plate and a wall defining the opening.

10. The semiconductor device according to claim 9, wherein the thermal insulation resin is arranged on the wiring substrate between the first semiconductor chip and the second semiconductor chip.