DISPLAY PANEL

• US 20130044046A1
• Filed: 05/15/2012
• Published: 02/21/2013
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: Ta-Wei Chiu
• Inventors: Yeh, Chia-Yuan, Chiu, Ta-Wei, Huang, Yen-Shih, Lee, Bo-Feng
• Granted Patent: US 9,070,897 B2
• Time in Patent Office: Days
• US Class Current: 345/76
• CPC Class Codes: H10K 50/841 Self-supporting sealing arrangements
• CPC Class Codes: H10K 59/124 Insulating layers formed between TFT elements and OLED elements
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/871 Self-supporting sealing arrangements

Abstract

A display panel includes a substrate, a TFT device, a patterned dielectric layer, a patterned metal layer and a bridge line. The TFT device is disposed in a display region. The patterned dielectric layer includes an ILD layer disposed over the TFT device, and a sealant stage disposed in a peripheral region. The patterned metal layer includes a signal line disposed on the ILD layer, and a first connecting line and a second connecting line. The first connecting line is disposed in an inner side of the sealant stage facing the display region, and the first connecting line is electrically connected to the signal line. The second connecting line is disposed in an outer side of the sealant stage opposite to the display region. The bridge line is disposed under the sealant stage, and the first connecting line and the second connecting line are electrically connected through the bridge line.

Claims

1. A display panel, comprising:

a substrate, having a display region and a peripheral region;

at least one thin film transistor device, disposed in the display region;

a patterned dielectric layer, comprising;

an inter-layered dielectric (ILD) layer, disposed in the display region and over the thin film transistor device; and

a sealant stage, disposed in the peripheral region and surrounding the display region;

a patterned metal layer, comprising;

at least one signal line, disposed on the ILD layer in the display region; and

at least one first connecting line and at least one second connecting line, disposed in the peripheral region, the first connecting line being disposed in an inner side of the sealant stage facing the display region and electrically connected to the signal line, and the second connecting line being disposed in an outer side of the sealant stage opposite to the display region; and

at least one bridge line, disposed in the peripheral region, the bridge line being disposed at least under the sealant stage, wherein the first connecting line and the second connecting line are electrically connected to each other through the bridge line.

2. The display panel of claim 1, wherein the bridge line is further disposed under the first connecting line and the second connecting line.

3. The display panel of claim 1, wherein the thin film transistor device comprises a top gate type thin film transistor device.

4. The display panel of claim 1, wherein the thin film transistor device comprises:

a semiconductor channel layer, disposed on the substrate;

two doped layers, disposed on the substrate and corresponding to two opposite sides of the semiconductor channel layer;

a gate insulating layer, disposed on the substrate, the semiconductor channel layer and the doped layers;

a gate electrode, disposed on the gate insulating layer; and

two source/drain electrodes, disposed on the ILD layer and electrically connected to the doped layers, respectively.

5. The display panel of claim 4, wherein the source/drain electrodes are made of the patterned metal layer, and the bridge line and the gate electrode are made of another patterned metal layer.

6. The display panel of claim 4, wherein the bridge line and the doped layers are made of a patterned doped layer.

7. The display panel of claim 1, further comprising:

a passivation layer, disposed on the ILD layer and the source/drain electrodes; and

a light-emitting device, disposed on the passivation layer, wherein the light-emitting device comprises a transparent electrode.

8. The display panel of claim 7, further comprising a transparent conductive pattern disposed on the first connecting line and the second connecting line in the peripheral region, wherein the transparent conductive pattern exposes the sealant stage, and electrically connects with the first connecting line and the second connecting line.

9. The display panel of claim 8, wherein the transparent electrode and the transparent conductive pattern are made of a patterned transparent conductive layer.

10. The display panel of claim 1, wherein the patterned dielectric layer comprises an inorganic dielectric layer, and the ILD layer and the sealant stage are made of a same film layer.

11. The display panel of claim 1, further comprising:

an encapsulation substrate, disposed opposite to the substrate; and

a sealant, disposed on the sealant stage, to bond the encapsulation substrate and the substrate.

12. The display panel of claim 11, wherein the sealant comprises a glass frit.