FORMING METHOD OF PERFORMING FORMING ON VARIABLE RESISTANCE NONVOLATILE MEMORY ELEMENT, AND VARIABLE RESISTANCE NONVOLATILE MEMORY DEVICE

• US 20130044534A1
• Filed: 03/28/2011
• Published: 02/21/2013
• Est. Priority Date: 03/30/2010
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Inventors: Kawai, Ken, Shimakawa, Kazuhiko, Katayama, Koji
• Granted Patent: US 8,848,421 B2
• Time in Patent Office: Days
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0073 Write using bi-directional cell biasing
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2213/32 Material having simple binary metal oxide structure
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/24 based on migration or redistribution of ionic species, e.g. anions, vacancies
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

A forming method of a variable resistance nonvolatile memory element capable of lowering a forming voltage and preventing variations of the forming voltage depending on variable resistance elements. The forming method is for initializing a variable resistance element, including a step (S24) of determining whether or not a current flowing in a 1T1R memory cell is greater than a reference current; a step (S22) of applying a forming positive voltage pulse having a pulse width (Tp(n)) is gradually increased when it is determined that the current is not greater than the reference current; and a step (S23) of applying a negative voltage pulse having a pulse width Tn equal to or shorter than a pulse width Tp(n). The determining step (S24), the application step (S22), and the application step (S23) are repeated until the forming becomes successful.

Claims

1-25. -25. (canceled)

26. A forming method of performing forming on a variable resistance nonvolatile memory element, by applying a voltage pulse to a memory cell in which the variable resistance nonvolatile memory element is connected in series with a switch element, so as to change a resistance state of the variable resistance nonvolatile memory element from an initial state after manufacturing to a changeable state, the initial state being higher than a high resistance state and having not yet been changed to the changeable state, and the changeable state being a state where the resistance state is reversibly changeable between the high resistance state and a low resistance state according to a polarity of an applied voltage pulse and being lower than the initial state,

the variable resistance nonvolatile memory element including:

a first electrode connected to the switch element;

a second electrode; and

an oxygen-deficient transition metal oxide layer provided between the first electrode and the second electrode,

the oxygen-deficient transition metal oxide layer including;

a first transition metal oxide layer in contact with the first electrode; and

a second transition metal oxide layer in contact with the second electrode, the second transition metal oxide layer having an oxygen deficient degree lower than an oxygen deficient degree of the first transition metal oxide layer,

the variable resistance nonvolatile memory element having;

characteristics by which the resistance state is changed to the low resistance state when a low resistance writing voltage pulse having a positive potential and equal to or higher than a first threshold voltage is applied to the first electrode with reference to the second electrode, and the resistance state is changed to the high resistance state when a high resistance writing voltage pulse having a positive potential and equal to or higher than a second threshold voltage is applied to the second electrode with reference to the first electrode;

non-linear current-voltage characteristics in the initial state; and

characteristics by which as a current flowing in the variable resistance nonvolatile memory element is increased in the initial state, a time period required for the forming is decreased in an exponential manner, and the forming method comprising;

applying a first voltage pulse to the variable resistance nonvolatile memory element when the variable resistance nonvolatile memory element is in the initial state, the first voltage pulse (1) having (1-i) a positive potential at the second electrode with reference to the first electrode and an amplitude equal to or greater than an amplitude of a predetermined voltage higher than the second threshold voltage or (1-ii) a negative potential at the second electrode with reference to the first electrode and an amplitude equal to or greater than an amplitude of a predetermined voltage higher than the first threshold voltage, and the first voltage pulse (2) having a first pulse width; and

determining whether or not the forming is successful by the applying of the first voltage pulse,

wherein the applying of the first voltage pulse and the determining are repeated until it is determined in the determining that the forming is successful, and

in the applying of the first voltage pulse in the repeating, a new first voltage pulse is applied to the variable resistance nonvolatile memory element, the new first voltage pulse having a pulse width longer than a pulse width of the first voltage pulse applied in the applying of the first voltage pulse which is performed immediately prior to the applying of the new first voltage pulse.

27. The forming method according to claim 26,

wherein in the applying of the first voltage pulse, as the first voltage pulse, a first positive voltage pulse is applied to the variable resistance nonvolatile memory element, the first positive voltage pulse (1) having an amplitude equal to or greater than an amplitude of the predetermined voltage having a positive potential at the second electrode with reference to the first electrode, and the first positive voltage pulse (2) having the first pulse width, and

in the determining, a first negative voltage pulse is applied to the variable resistance nonvolatile memory element, the first negative voltage pulse (1) having a voltage amplitude equal to or greater than a voltage amplitude of the low resistance writing voltage pulse, and the first negative voltage pulse (2) having a same polarity as a polarity of the low resistance writing voltage pulse, and after the applying of the first negative voltage pulse, it is determined whether or not the variable resistance nonvolatile memory element is in the low resistance state, so as to determine whether or not the forming is successful.

28. The forming method according to claim 26,

wherein in the applying of the first voltage pulse in the repeating, the new first voltage pulse is applied to the variable resistance nonvolatile memory element, the new first voltage pulse having the pulse width that is increased in an exponential manner from the pulse width of the first voltage pulse applied in the applying of the first voltage pulse which is performed immediately prior to the applying of the new first voltage pulse.

29. The forming method according to claim 27,

wherein a pulse width of the first negative voltage pulse is equal to a pulse width of the low resistance writing voltage pulse.

30. The forming method according to claim 27, further comprising

applying a second positive voltage pulse to the variable resistance nonvolatile memory element after the applying of the first negative voltage pulse in the determining, the second positive voltage pulse having a polarity, a voltage amplitude, and a pulse width which are equal to a polarity, the amplitude, and the first pulse width of the first positive voltage pulse, respectively.

31. The forming method according to claim 30,

wherein a pulse width of the first negative voltage pulse is longer than a pulse width of the low resistance writing voltage pulse.

32. The forming method according to claim 26,

wherein a material of the first electrode is different from a material of the second electrode, and

the second electrode comprises one of:

iridium; and

an alloy of Ir and platinum.

33. The forming method according to claim 26,

wherein the first transition metal oxide layer comprises a composition expressed by TaO_x, and

the second transition metal oxide layer comprises a composition expressed by TaO_y, where x<

y.

34. The forming method according to claim 26,

wherein a transition metal included in the first transition metal oxide layer is different from a transition metal included in the second transition metal oxide layer.

35. The forming method according to claim 26,

wherein the variable resistance nonvolatile memory element in the initial state has an initial resistance value that is higher than a resistance value of the variable resistance nonvolatile memory element in the high resistance state, and

the initial resistance value is higher than 1 MΩ

.

36. The forming method according to claim 26,

wherein the switch element is a MOS transistor.

37. The forming method according to claim 26,

wherein the switch element is a bi-directional diode.

38. A variable resistance nonvolatile memory device including memory cells in each of which a variable resistance nonvolatile memory element is connected in series with a switch element,

the variable resistance nonvolatile memory element including:

a first electrode connected to the switch element;

a second electrode; and

an oxygen-deficient transition metal oxide layer provided between the first electrode and the second electrode,

the oxygen-deficient transition metal oxide layer including;

a first transition metal oxide layer in contact with the first electrode; and

a second oxygen-deficient transition metal oxide layer in contact with the second electrode, the second oxygen-deficient transition metal oxide layer having an oxygen deficient degree lower than an oxygen deficient degree of the first transition metal oxide layer,

the variable resistance nonvolatile memory element having;

characteristics by which a resistance state of the variable resistance nonvolatile memory element is changed to the low resistance state when a low resistance writing voltage pulse having a positive voltage and equal to or higher than a first threshold voltage is applied to the first electrode with reference to the second electrode, and the resistance state is changed to a high resistance state when a high resistance writing voltage pulse having a positive voltage and equal to or higher than a second threshold voltage is applied to the second electrode with reference to the first electrode;

non-linear current-voltage characteristics in an initial state after manufacturing where the resistance state is higher than the high resistance sate and has not yet been changed to a changeable state where the resistance state is reversibly changeable between the high resistance state and the low resistance state according to a polarity of an applied voltage pulse and is lower than the initial state; and

characteristics by which (i) when a voltage pulse of a voltage equal to or higher than a predetermined voltage is applied in the initial state and is kept being applied for a predetermined time period, forming occurs to change the resistance state from the initial state to the changeable state, and (ii) as a current flowing in the variable resistance nonvolatile memory element is increased, a time period required for the forming is decreased in an exponential manner, and

the variable resistance nonvolatile memory device comprising;

a memory cell array including the memory cells in each of which the variable resistance nonvolatile memory element is connected in series with the switch element;

a selection unit configured to select at least one memory cell from the memory cell array;

a forming power source unit configured to generate a forming voltage to perform the forming on the variable resistance nonvolatile memory element included in the at least one memory cell selected by the selection unit;

a writing power source unit configured to generate a writing voltage to perform writing to change the resistance state of the variable resistance nonvolatile memory element included in the at least one memory cell selected by the selection unit from the high resistance state to the low resistance state or from the low resistance state to the high resistance state;

a variable pulse width writing voltage pulse generation unit configured to generate a writing voltage pulse having a variable pulse width to change the resistance state of the variable resistance nonvolatile memory element to a desired state, when one of the forming and the writing is performed on the variable resistance nonvolatile memory element included in the at least one memory cell selected by the selection unit; and

a reading unit including (a) a forming determination unit configured to determine whether or not the forming is successful on the variable resistance nonvolatile memory element included in the at least one memory cell selected by the selection unit and (b) a normal determination unit configured to determine whether or not the variable resistance nonvolatile memory element included in the at least one memory cell selected by the selection unit is in the high resistance state or in the low resistance state,

wherein the variable pulse width writing voltage pulse generation unit is configured, for the forming on the variable resistance nonvolatile memory element, to apply a first voltage pulse to the variable resistance nonvolatile memory element, the first voltage pulse (1) having (1-i) a positive potential at the second electrode with reference to the first electrode and an amplitude equal to or greater than an amplitude of a predetermined voltage higher than the second threshold voltage or (1-ii) a negative potential at the second electrode with reference to the first electrode and an amplitude equal to or greater than an amplitude of a predetermined voltage higher than the first threshold voltage, and the first voltage pulse (2) having a first pulse width, the application by the variable pulse width writing voltage pulse generation unit and the determination by the forming determination unit are repeated until the forming determination unit determines that the forming is successful, and

in the repetition, the variable pulse width writing voltage pulse generation unit is configured to apply a new first voltage pulse to the variable resistance nonvolatile memory element, the new first voltage pulse having a pulse width longer than a pulse width of the first voltage pulse applied immediately prior to the new first voltage pulse.

39. The variable resistance nonvolatile memory device according to claim 38,

wherein the variable pulse width writing voltage pulse generation unit is configured to apply a first positive voltage pulse, as the first voltage pulse, to the variable resistance nonvolatile memory element, the first positive voltage pulse (1) having a positive potential at the second electrode with reference to the first electrode and an amplitude equal to or greater than an amplitude of the predetermined voltage, and the first positive voltage pulse (2) having the first pulse width, and

the forming determination unit is configured to determine whether or not the variable resistance nonvolatile memory element is in the low resistance state, so as to determine whether or not the forming of the variable resistance nonvolatile memory element after the application of the first positive voltage pulse is successful.

40. The variable resistance nonvolatile memory device according to claim 39,

wherein the forming determination unit is configured to (i) apply a first negative voltage pulse to the variable resistance nonvolatile memory element, the first negative voltage pulse (1) having a voltage amplitude equal to or greater than a voltage amplitude of the low resistance writing voltage pulse, and the first negative voltage pulse (2) having a same polarity as a polarity of the low resistance writing voltage pulse, and (ii) determine, after the application of the first negative voltage pulse, whether or not the variable resistance nonvolatile memory element is in the low resistance state.

41. The variable resistance nonvolatile memory device according to claim 40,

wherein a pulse width of the first negative voltage pulse is equal to a pulse width of the low resistance writing voltage pulse.

42. The variable resistance nonvolatile memory device according to claim 38,

wherein a material of the first electrode is different from a material of the second electrode, and

the second electrode comprises one of:

iridium; and

an alloy of Ir and platinum.

43. The variable resistance nonvolatile memory device according to claim 38,

wherein the first transition metal oxide layer comprises a composition expressed by TaO_x, and

the second oxygen-deficient transition metal oxide layer comprises a composition expressed by TaO_y, where x<

y.

44. The variable resistance nonvolatile memory device according to claim 38,

wherein a transition metal included in the first transition metal oxide layer is different from a transition metal included in the second oxygen-deficient transition metal oxide layer.

45. The variable resistance nonvolatile memory device according to claim 38,

wherein the variable resistance nonvolatile memory element in the initial state has an initial resistance value that is higher than a resistance value of the variable resistance nonvolatile memory element in the high resistance state, and

the initial resistance value is higher than 1 MΩ

.

46. The variable resistance nonvolatile memory device according to claim 38,

wherein the switch element has (a) current driving performance that is greater in the application of a voltage pulse having a positive potential at the second electrode with reference to the first electrode to the variable resistance nonvolatile memory element than (b) current driving performance in the application of a voltage pulse having a negative potential at the second electrode with reference to the first electrode to the variable resistance nonvolatile memory element.

47. The variable resistance nonvolatile memory device according to claim 38,

wherein the switch element is a MOS transistor.

48. The variable resistance nonvolatile memory device according to claim 38,

wherein the switch element is a bi-directional diode.

49. The variable resistance nonvolatile memory device according to claim 38,

wherein the selection unit is configured to sequentially select all of the memory cells included in the memory cell array, and

the variable pulse width writing voltage pulse generation unit is configured to apply, after the application of the first voltage pulse to variable resistance nonvolatile memory elements included in the all of the memory cells selected by the selection unit, the new first voltage pulse to a memory cell including a variable resistance nonvolatile memory element determined by the forming determination unit as not being successful in the forming from among the all of the memory cells selected by the selection unit.

50. A variable resistance nonvolatile memory element connected in series with a switch element to form a memory cell, the variable resistance nonvolatile memory element comprising:

a first electrode connected to the switch element;

a second electrode; and

an oxygen- deficient transition metal oxide layer provided between the first electrode and the second electrode,

wherein the oxygen-deficient transition metal oxide layer includes;

a first transition metal oxide layer in contact with the first electrode; and

a second transition metal oxide layer in contact with the second electrode, the second transition metal oxide layer having an oxygen deficient degree lower than an oxygen deficient degree of the first transition metal oxide layer, and

the variable resistance nonvolatile memory element has;

characteristics by which a resistance state of the variable resistance nonvolatile memory element is changed to a low resistance state when a low resistance writing voltage pulse having a positive potential and equal to or higher than a first threshold voltage is applied to the first electrode with reference to the second electrode, and the resistance state is changed to a high resistance state when a high resistance writing voltage pulse having a positive potential and equal to or higher than a second threshold voltage is applied to the second electrode with reference to the first electrode;

an initial state after manufacturing where the resistance state is higher than the high resistance state and has not yet been changed to a changeable state where the resistance state is reversibly changeable between the high resistance state and the low resistance state according to a polarity of an applied voltage pulse and is lower than the initial state;

non-linear current-voltage characteristics in the initial state;

characteristics by which (i) when a voltage pulse of a voltage equal to or higher than a predetermined voltage is applied in the initial state and is kept being applied for a predetermined time period, forming occurs to change the resistance state to the changeable state, and (ii) as a current flowing in the variable resistance nonvolatile memory element is increased, a time period required for the forming is decreased in an exponential manner; and

characteristics, in the forming, by which as a cumulative pulse application time period of at least one applied voltage pulse is increased, a probability that the forming is successful is increased.