NON-VOLATILE MEMORY DEVICE HAVING VERTICAL STRUCTURE AND METHOD OF OPERATING THE SAME

• US 20130044545A1
• Filed: 10/23/2012
• Published: 02/21/2013
• Est. Priority Date: 02/02/2009
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jae-Hoon Jang, Jae-Hun Jeong, Sun-Il Shim, Won-Seok Cho
• Inventors: Jeong, Jae-hun, Kim, Han-soo, Cho, Won-seok, Jang, Jae-hoon, Shim, Sun-il
• Application Number:
  US13/658,461
• Publication Number:
  US 20130044545A1
• Time in Patent Office: Days
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels

Abstract

A non-volatile memory device having a vertical structure includes a NAND string having a vertical structure. The NAND string includes a plurality of memory cells, and at least one pair of first selection transistors arranged to be adjacent to a first end of the plurality of memory cells. A plurality of word lines are coupled to the plurality of memory cells of the NAND string. A first selection line is commonly connected to the at least one pair of first selection transistors of the NAND string.

Claims

1. A method of operating a non-volatile memory device, the method comprising:

applying a program voltage to one memory cell selected from among a plurality of memory cells arranged in series of a NAND string from a plurality of vertically arranged NAND strings, and applying a pass voltage to the remaining memory cells of the NAND string, where the pass voltage is less than the program voltage; and

applying a first voltage to a first selection transistor closest to the plurality of memory cells in the NAND string, the first selection transistor from a pair of first selection transistors that is adjacent to the plurality of memory cells in the NAND string, and applying a second voltage to a remaining first selection transistor from the pair of first selection transistors, where the second voltage is different from the first voltage.

2. The method of claim 1, wherein the first voltage is substantially equal to the pass voltage.

3. The method of claim 1, wherein the second voltage is equal to or greater than a threshold voltage of the remaining first selection transistor.

4. The method of claim 1, further comprising applying 0V to a pair of second selection transistors that is adjacent to the plurality of memory cells in the NAND string and opposite to the pair of first selection transistors.

5. The method of claim 1, further comprising applying 0V to a bit line connected to a first end of one of the plurality of NAND strings so that data stored in a memory cell selected from among the plurality of memory cells of the NAND string is programmed.

6. The method of claim 1, further comprising applying an operational voltage to a bit line connected to a first end of one of the plurality of NAND strings to prevent data stored in the plurality of memory cells of the NAND string from being programmed.

7. The method of claim 1, where the second voltage is less than the first voltage.

8. A method of operating a non-volatile memory device, the method comprising:

applying a program voltage to one memory cell selected from among a plurality of memory cells arranged in series of a NAND string from a plurality of vertically arranged NAND strings, and applying a pass voltage to the remaining memory cells of the NAND string, where the pass voltage is less than the program voltage; and

applying a first voltage to a pair of first selection transistors closest to the plurality of memory cells in the NAND string.

9. The method of claim 8, further comprising applying a second voltage to a pair of second selection transistors that is adjacent to the plurality of memory cells in the NAND string and opposite to the pair of first selection transistors.

10. The method of claim 8, wherein the pass voltage is greater than a threshold voltage of the memory cells.

11. The method of claim 8, wherein the first voltage is equal to or greater than a threshold voltage of the pair of first selection transistors.

12. The method of claim 9, wherein the second voltage is less than a threshold voltage of the pair of second selection transistors.

13. The method of claim 8, further comprising applying 0V to a bit line connected to a first end of one of the plurality of NAND strings so that data stored in a memory cell selected from among the plurality of memory cells of the NAND string is programmed.

14. A method of operating a non-volatile memory device having a control logic unit and a row decoder, the method comprising:

applying a program voltage to one memory cell selected from among a plurality of memory cells arranged in series of a NAND string from a plurality of vertically arranged NAND strings, and applying a pass voltage to the remaining memory cells of the NAND string, where the pass voltage is less than the program voltage; and

applying a first voltage to at least one first selection transistor closest to the plurality of memory cells in the NAND string, and applying a second voltage to at least one second selection transistor that is adjacent to the plurality of memory cells in the NAND string and opposite to the first selection transistor,

wherein applying the second voltage to the at least one second selection transistor further comprises;

transmitting a row address signal from the control logic unit to the row decoder, and applying the second voltage from the row decoder to the at least one ground selection line coupled to the at least one second selection transistor.

15. The method of claim 14, wherein the at least one first selection transistor corresponds a pair of first selection transistors.

16. The method of claim 14, wherein the at least one second selection transistor corresponds a pair of second selection transistors.

17. The method of claim 16, wherein the pair of second selection transistors commonly couples the one ground selection line.

18. The method of claim 16, wherein the at least one ground selection line corresponds a pair of ground selection lines, and the pair of second selection transistors is correspondingly couples the pair of ground selection lines.