METHODS FOR FABRICATING FINFET INTEGRATED CIRCUITS IN BULK SEMICONDUCTOR SUBSTRATES

• US 20130045580A1
• Filed: 08/15/2011
• Published: 02/21/2013
• Est. Priority Date: 08/15/2011
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Advanced Technologies Inc. (f/k/a Tessera Advanced Technologies, Inc.) (Adeia Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Cho, Jin
• Granted Patent: US 8,461,008 B2
• Time in Patent Office: Days
• US Class Current: 438/296
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

Methods are provided for fabricating FinFETs that avoid thickness uniformity problems across a die or a substrate. One method includes providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines. The substrate is etched to form a plurality of fins, each of the fins extending uniformly across the width of the chips. An oxide is deposited to fill between the fins and is etched to recess the top of the oxide below the top of the fins. An isolation hard mask is deposited and patterned overlying the plurality of fins and is used as an etch mask to etch trenches in the substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins. The trenches are filled with an insulating material to isolate between adjacent active areas.

Claims

1. A method for fabricating a FinFET integrated circuit comprising:

providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines;

etching the semiconductor substrate to form a plurality of fins, each of the plurality of fins extending across the width of the chips substantially to the scribe lines;

depositing an oxide to fill between the fins;

etching the oxide to recess the oxide;

depositing and patterning an isolation hard mask overlying the plurality of fins;

etching the semiconductor substrate using the isolation hard mask as an etch mask to form trenches in the semiconductor substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins; and

filling the trenches with an insulating material to isolate between adjacent ones of the plurality of active areas.

2. The method of claim 1 wherein etching the semiconductor substrate comprises:

depositing and patterning a layer of hard mask material to form a plurality of hard mask lines having substantially uniform pitch and spacing;

anisotropically etching the semiconductor substrate using plurality of hard mask lines as an etch mask to form the plurality of fins.

3. The method of claim 2 wherein depositing an oxide comprises:

depositing a layer of oxide overlying the plurality of hard mask lines and the plurality of fins and filling between the plurality of fins;

planarizing the layer of oxide using the plurality of hard mask lines as a planarization stop; and

further planarizing to remove the plurality of hard mask lines and to stop substantially at the plurality of fins.

4. The method of claim 1 wherein etching the semiconductor substrate comprises etching the semiconductor substrate to form fins having a height of 40-100 nm and a width of 10-20 nm.

5. The method of claim 1 wherein etching the oxide comprises etching the oxide to expose 10-30 nm of the plurality of fins.

6. The method of claim 1 further comprising oxidizing the plurality of fins after etching the oxide and before depositing and patterning an isolation hard mask.

7. The method of claim 1 wherein filling the trenches comprises:

depositing a trench liner;

depositing a gap fill oxide overlying the trench liner;

planarizing the gap fill oxide and stopping the planarization on the isolation hard mask;

etching the gap fill oxide to recess the gap fill oxide to substantially the height of the oxide between the plurality of fins; and

removing the isolation hard mask.

8. The method of claim 1 further comprising:

forming a gate insulator overlying the at least a portion of at least one of the plurality of fins; and

forming a gate electrode overlying the gate insulator.

9. The method of claim 8 further comprising impurity doping source and drain regions in the at least a portion of at least one of the plurality of fins in self alignment with the gate electrode.

10. A method for fabricating a FinFET integrated circuit comprising:

providing a semiconductor substrate divided into a plurality of chip areas;

etching the semiconductor substrate to form a plurality of fins extending across each chip area;

forming isolation between adjacent ones of the plurality of fins;

etching through the plurality of fins and into the semiconductor substrate to form trenches in the semiconductor substrate and to divide the plurality of fins into fins of predetermined length; and

filling the trenches with insulating material.

11. The method of claim 10 wherein etching the semiconductor substrate comprises:

forming a silicon nitride hard mask overlying the semiconductor substrate; and

anisotropically etching the semiconductor substrate using the hard mask as an etch mask.

12. The method of claim 11 wherein forming isolation comprises:

depositing a layer of oxide overlying the plurality of fins;

planarizing the layer of oxide by chemical mechanical planarization and stopping the planarization on the hard mask; and

etching the planarized layer of oxide to recess the top of the oxide below the top of the plurality of fins.

13. The method of claim 11 wherein forming isolation comprises:

depositing a layer of oxide overlying the plurality of fins;

planarizing the layer of oxide and removing the hard mask by chemical mechanical planarization and stopping the planarization at the top of the plurality of fins; and

etching the planarized layer of oxide to recess the top of the oxide below the top of the plurality of fins.

14. The method of claim 10 further comprising forming gate structures overlying the fins of predetermined length.

15. A method for fabricating a FinFET integrated circuit comprising:

providing a silicon substrate divided into a plurality of chip areas;

etching the silicon substrate to form a uniform array of fins extending across each of the chip areas;

depositing a layer of oxide overlying the array of fins;

planarizing the layer of oxide;

etching the silicon substrate and the uniform array of fins to define a plurality of active areas, each active area including at least a portion of a fin of the uniform array of fins; and

forming isolation between the plurality of active areas.

16. The method of claim 15 wherein etching the silicon substrate and the uniform array of fins comprises etching trenches into the silicon substrate and wherein forming isolation between the active areas comprises filling the trenches with insulating material.

17. The method of claim 15 further comprising:

after planarizing the layer of oxide, etching the layer of oxide to recess the top of the oxide below the top of the array of fins; and

thermally oxidizing the fins of the array of fins to form an oxide on the surface of each of the fins.

18. The method of claim 15 further comprising:

forming a gate structure overlying the at least a portion of the fin; and

impurity doping source and drain regions of the at least a portion of the fin in self alignment with the gate structure.

19. The method of claim 15 wherein etching the silicon substrate to form a uniform array comprises:

patterning an etch mask overlying the silicon substrate; and

anisotropically etching the silicon substrate to form the array of fins, each of the fins of the array having substantially equal widths and substantially equal spacing.

20. The method of claim 19 wherein anisotropically etching comprises etching the silicon substrate to form fins having substantially equal widths of 10-20 nm and a pitch of 40-60 nm.