FLASH MEMORY CONTROLLER

• US 20130046917A1
• Filed: 06/07/2012
• Published: 02/21/2013
• Est. Priority Date: 08/19/2011
• Status: Active Grant

• Current Assignee: Silicon Motion Incorporated California (Silicon Motion)
• Original Assignee: Tsung-Chieh Yang
• Inventors: YANG, Tsung-Chieh, Lin, Ching-Hui, Shen, Yang-Chih, Kuo, Chun-Chieh
• Granted Patent: US 9,075,709 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory controller includes a recording medium and a processing circuit. When the amount of stored data in a flash memory module is less than a first threshold, the processing circuit controls a read and write circuit of the flash memory module to program a target data block using program threshold voltages within a first voltage range so as to write data into the target data block. When the amount of stored data in the flash memory module is greater than a second threshold, the processing circuit controls the read and write circuit to program the target data block using program threshold voltages within a second voltage range so as to write data into the target data block, wherein the second threshold is greater than the first threshold and the first voltage range is less than 50% of the second voltage range.

Claims

1. A flash memory controller comprising:

a communication interface for receiving a first data, a second data, and a third data;

a recording medium for recording an amount of stored data in a flash memory module, wherein the flash memory module comprising a read and write circuit, a first data block, a second data block, and a third data block; and

a processing circuit, coupled with the communication interface, the recording medium, and the flash memory module, for controlling the read and write circuit to configure program threshold voltages of at least one cell in the first data block to be within a first voltage range so as to write the first data into the first data block when the amount of stored data in a flash memory module is less than a first threshold, and for controlling the read and write circuit to configure program threshold voltages of at least one cell in the third data block to be within a second voltage range so as to write the third data into the third data block when the amount of stored data in the flash memory module is greater than a second threshold;

wherein the second threshold is greater than the first threshold and the first voltage range is less than 50% of the second voltage range.

2. The flash memory controller of claim 1, wherein an upper limit of the first voltage range is less than 80% of an upper limit of the second voltage range.

3. The flash memory controller of claim 1, wherein an upper limit of the first voltage range is less than 60% of an upper limit of the second voltage range.

4. The flash memory controller of claim 1, wherein an upper limit of the first voltage range is less than 30% of an upper limit of the second voltage range.

5. The flash memory controller of claim 1, wherein the communication interface further receives a fourth data, and if the fourth data is not cold data, the processing circuit decides a range of program threshold voltages for cells in a data block for use to store the fourth data according to the amount of stored data in the flash memory module.

6. The flash memory controller of claim 5, wherein the communication interface further receives a fifth data, and if the fifth data is not hot data, the processing circuit decides a range of program threshold voltages for cells in a data block for use to store the fifth data according to the amount of stored data in the flash memory module.

7. The flash memory controller of claim 1, wherein the communication interface further receives a fifth data, and if the fifth data is not hot data, the processing circuit decides a range of program threshold voltages for cells in a data block for use to store the fifth data according to the amount of stored data in the flash memory module.

8. The flash memory controller of claim 1, wherein when the second data is received by the communication interface, if the amount of stored data in the flash memory module is between the first threshold and the second threshold, the processing circuit controls the read and write circuit to configure program threshold voltages of at least one cell in the second data block to be within a third voltage range so as to write the second data into the second data block;

wherein the third voltage range is less than 60% of the second voltage range.

9. The flash memory controller of claim 8, wherein an upper limit of the third voltage range is less than 80% of an upper limit of the second voltage range.

10. The flash memory controller of claim 8, wherein an upper limit of the third voltage range is less than 60% of an upper limit of the second voltage range.

11. The flash memory controller of claim 8, wherein the processing circuit controls the read and write circuit to write the first data into the first data block under an one-bit-per-cell mode, to write the second data into the second data block under a two-bit-per-cell mode, and to write the third data into the third data block under a three-bit-per-cell mode.

12. The flash memory controller of claim 11, wherein the processing circuit selects the first, second, and third data blocks from the flash memory module according to at least one of a number of times each data block was written under the one-bit-per-cell mode, a number of times each data block was written under the two-bit-per-cell mode, and a number of times each data block was written under the three-bit-per-cell mode.

13. The flash memory controller of claim 11, wherein when an amount of data blocks in use within the flash memory module is higher than a third threshold or when an amount of empty data blocks within the flash memory module is lower than a fourth threshold, the processing circuit controls the read and write circuit to write valid data, stored in one or more candidate data blocks containing data written under the one-bit-per-cell mode, into a target data block under the two-bit-per-cell mode or the three-bit-per-cell mode, and to erase the candidate data blocks.

14. The flash memory controller of claim 11, wherein when an amount of data blocks in use within the flash memory module is higher than a third threshold or when an amount of empty data blocks within the flash memory module is lower than a fourth threshold, the processing circuit controls the read and write circuit to write valid data, stored in one or more candidate data blocks containing data written under the two-bit-per-cell mode, into a target data block under the three-bit-per-cell mode, and to erase the candidate data blocks.

15. A flash memory controller comprising:

a recording medium for recording an amount of stored data in a flash memory module, wherein the flash memory module comprising a read and write circuit and a target data block; and

a processing circuit, coupled with the recording medium and the flash memory module, for controlling the read and write circuit to program cells in the target data block using program threshold voltages within a first voltage range so as to write data into the target data block when the amount of stored data in a flash memory module is less than a first threshold, and for controlling the read and write circuit to program the cells in the target data block using program threshold voltages within a second voltage range so as to write data into the target data block when the amount of stored data in the flash memory module is greater than a second threshold;

wherein the second threshold is greater than the first threshold and the first voltage range is less than 50% of the second voltage range.

16. The flash memory controller of claim 15, wherein an upper limit of the first voltage range is less than 80% of an upper limit of the second voltage range.

17. The flash memory controller of claim 15, wherein an upper limit of the first voltage range is less than 60% of an upper limit of the second voltage range.

18. The flash memory controller of claim 15, wherein an upper limit of the first voltage range is less than 30% of an upper limit of the second voltage range.

19. The flash memory controller of claim 15, wherein when the amount of stored data in the flash memory module is between the first threshold and the second threshold, the processing circuit controls the read and write circuit to program cells in the target data block using program threshold voltages within a third voltage range so as to write data into the target data block;

wherein the third voltage range is less than 60% of the second voltage range.

20. The flash memory controller of claim 19, wherein an upper limit of the third voltage range is less than 80% of an upper limit of the second voltage range.

21. The flash memory controller of claim 19, wherein an upper limit of the third voltage range is less than 60% of an upper limit of the second voltage range.

22. A flash memory controller comprising:

a recording medium for recording an amount of data blocks in use within a flash memory module, wherein the flash memory module comprising a read and write circuit and a plurality of data blocks; and

a processing circuit, coupled with the recording medium and the flash memory module, for, when an amount of data blocks in use within the flash memory module is higher than a third threshold or when an amount of empty data blocks within the flash memory module is lower than a fourth threshold, controlling the read and write circuit to write valid data stored in a plurality of candidate data blocks into a target data block and to erase the plurality of candidate data blocks;

wherein at least one cell of the plurality of candidate data blocks has a program threshold voltage configured to be within a first voltage range before erasing, and the first voltage range is less than 50% of the second voltage range.

23. The flash memory controller of claim 22, wherein an upper limit of the first voltage range is less than 80% of an upper limit of the second voltage range.

24. The flash memory controller of claim 22, wherein an upper limit of the first voltage range is less than 60% of an upper limit of the second voltage range.

25. The flash memory controller of claim 22, wherein an upper limit of the first voltage range is less than 30% of an upper limit of the second voltage range.