NON-VOLATILE MEMORY SYSTEM

• US 20130046919A1
• Filed: 07/31/2012
• Published: 02/21/2013
• Est. Priority Date: 08/18/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Bong-Gwan Seol, Hee-Tak Shin, Jun-Seok Park, Wan-Soo Choi, Won-Jin Lim
• Inventors: Park, Jun-seok, Choi, Wan-soo, Shin, Hee-tak, Lim, Won-jin, Seol, Bong-gwan
• Granted Patent: US 8,984,212 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7207 management of metadata or control data

Abstract

In one embodiment, a memory system includes a memory device with a first memory and a second memory, and a controller configured to control storing of data in the memory device. The controller is configured to control an (N−1)^th piece of meta data to be stored in the second memory when an N^th piece of user data is stored in the first memory or control the N^th piece of the user data to be stored in the second memory when the (N−1)^th piece of the meta data is stored in the first memory, where N denotes a natural number equal to or greater than ‘1’. Also, a time period of storing the N^th piece of the user data is controlled to partially or entirely overlap with a time period of storing the (N−1)^th piece of the meta data.

Claims

1. A memory system, comprising:

a memory device including a first memory and a second memory; and

a controller configured to control storing of data in the memory device such that the controller controls an (N−

1)^th piece of meta data to be stored in the second memory when an N^th piece of user data is stored in the first memory or controls the N^th piece of the user data to be stored in the second memory when the (N−

1)^th piece of the meta data is stored in the first memory, where N denotes a natural number equal to or greater than ‘

1’

, and a time period of storing the N^th piece of the user data partially or entirely overlaps with a time period of storing the (N−

1)^th piece of the meta data.

2. The memory system of claim 1, wherein the (N−

1)^th piece of the meta data includes mapping information between a logical address and a physical address of the (N−

1)^th piece of the meta data.

3. The memory system of claim 1, wherein the controller comprises:

a processor configured to control transmitting of data to the memory device; and

a data buffer configured to temporarily store the N^th piece of the user data and the (N−

1)^th piece of the meta data,

wherein the memory device further comprises a data bus via which data is transmitted to the first memory and the second memory.

4. The memory system of claim 3, wherein the processor is configured to control the N^th piece of the user data to be transmitted from the data buffer to the first memory and then to control the (N−

1)^th piece of the meta data to be transmitted from the data buffer to the second memory, via the data bus.

5. The memory system of claim 3, wherein the processor is configured to control the (N−

1)^th piece of the meta data to be transmitted from the data buffer to the first memory and then to control the N^th piece of the user data to be transmitted from the data buffer to the second memory, via the data bus.

6. The memory system of claim 3, wherein the processor is configured to control the N^th piece of the user data to be stored in the first memory or the second memory, and then to control the (N−

1)^th piece of the meta data, which contains information regarding the N^th piece of the user data, to be temporarily stored in the data buffer.

7. The memory system of claim 1, wherein the controller comprises:

a processor configured to control transmitting of data to the memory device; and

a first data buffer and a second data buffer configured to temporarily store the N^th piece of the user data and the (N−

1)^th piece of the meta data, respectively; and

the memory device includes,

a first data bus via which data is transmitted to the first memory; and

a second data bus via which data is transmitted to the second memory.

8. The memory system of claim 7, wherein the processor is configured to simultaneously transmit the N^th piece of the user data temporarily stored in the first data buffer and the (N−

1)^th piece of the meta data temporarily stored in the second data buffer to the first memory and the second memory, respectively, via the first data bus and the second data bus.

9. The memory system of claim 7, wherein the processor is configured to control the N^th piece of the user data to be stored in the first memory or the second memory, and then to control the (N−

1)^th piece of the meta data, which contains information regarding the N^th piece of the user data, to be temporarily stored in the first or second data buffer.

10. The memory system of claim 1, wherein the controller is configured to store the (N−

1^th piece of the meta data in the first or second memory that stores an (N−

1)^th piece of the user data.

11. (canceled)

12. A storage device comprising:

a non-volatile memory device including at least one non-volatile memory with a first plane and a second plane; and

a controller configured to store data in the at least one non-volatile memory, the controller configured to one of (i) store meta data, which contains address information of previous user data stored in the at least one non-volatile memory in the second plane when user data is stored in the first plane and (ii) store the user data in the second plane when the meta data is stored in the first plane, and a time period of storing the user data partially or entirely overlapping with a time period of storing the meta data.

13. The storage device of claim 12, wherein the controller comprises:

a processor configured to control transmitting of data to the memory device; and

a data buffer configured to temporarily store the user data and the meta data;

wherein

the memory device further includes a data bus via which data is transmitted to the at least one non-volatile memory, and

the processor is configured to control the user data to be transmitted from the data buffer to the first plane and then is configured to control the meta data to be transmitted from the data buffer to the second plane, via the data bus.

14. The storage device of claim 13, wherein the processor is configured to control the meta data to be transmitted from the data buffer to the first plane and then control the user data to be transmitted from the data buffer to the second plane, via the data bus.

15. The storage device of claim 12, wherein the memory is a flash memory, and

the first plane and the second plane share a word line.

16. A memory system comprising:

a memory device; and

a controller configured to store user data and meta data in the memory device such that a time period for storing the user data at least partially overlaps with a time period for storing the meta data.

17. The memory system of claim 16, wherein

storing the user data includes transmitting the user data to the memory device and writing the user data into the memory device;

and

storing the meta data includes transmitting the meta data to the memory device and storing the meta data in the memory device.

18. The memory system of claim 17, wherein the controller is configured to store the user data and the meta data such that a time period to write the user data into the memory device at least partially overlaps with a time period to transmit the meta data to the memory device.

19. The memory system of claim 17, wherein the controller is configured to store the user data and the meta data such that a time period to write the meta data into the memory device at least partially overlaps with a time period to transmit the user data to the memory device.

20. The memory system of claim 17, wherein the controller is configured to store the user data and the meta data such that a time period to write the user data into the memory device at least partially overlaps with a time period to write the meta data into the memory device.

21. The memory system of claim 16, wherein controller is configured to store the user data and the meta data such that one of (i) the time period to store the user data entirely overlaps with the time period to store the meta data, and (ii) the time period to store the meta data entirely overlaps with the time period to store the user data.