Arrays Of Recessed Access Devices, Methods Of Forming Recessed Access Gate Constructions, And Methods Of Forming Isolation Gate Constructions In The Fabrication Of Recessed Access Devices

• US 20130049072A1
• Filed: 08/25/2011
• Published: 02/28/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Heineck, Lars P., Sorensen, Troy R.
• Granted Patent: US 9,385,132 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 21/28123 Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383

Abstract

A method of forming an array of recessed access device gate constructions includes using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array. The etch mask is used while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings. Individual recessed access gate constructions are formed in the individual recessed access device trenches. Other methods are contemplated, including arrays of recessed access devices independent of method of manufacture.

Claims

1. A method of forming an array of recessed access device gate constructions, comprising:

using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array;

using the etch mask while etching all of the recessed access device trenches into the semiconductor material within all of the array through the mask openings; and

forming individual recessed access gate constructions in the individual recessed access device trenches.

2. The method of claim 1 wherein the recessed access device gate constructions individually comprise a conductive gate having an elevationally outermost conductive surface, the elevationally outermost conductive surfaces of all of the conductive gates of the recessed access device gate constructions within all of the array relative one another being within no greater than 50 Angstroms of elevational thickness of the semiconductor material.

3. The method of claim 1 comprising forming individual isolation gate constructions in individual isolation trenches formed in the semiconductor material.

4. A method of forming an array of recessed access device gate constructions and isolation gate constructions, comprising:

using the width of an anisotropically etched sidewall spacer in forming first mask openings in an etch mask for forming all recessed access device trenches within semiconductor material within all of the array;

using space between anisotropically etched sidewall spacers in forming second mask openings in the etch mask for forming isolation trenches within the semiconductor material within the array;

using the etch mask while simultaneously etching the isolation trenches into the semiconductor material within the array through the second mask openings and all of the recessed access device trenches into the semiconductor material within all of the array through the first mask openings, the isolation trenches being formed deeper into the semiconductor material than are the recessed access device trenches; and

forming individual isolation gate constructions in the individual isolation trenches and individual recessed access gate constructions in the individual recessed access device trenches.

5. The method of claim 4 comprising using anisotropically etched sidewall spacer material in forming a hard-mask having features over which the anisotropically etched sidewall spacers are formed.

6. The method of claim 4 comprising forming the etch mask in hard-mask material underlying the anisotropically etched sidewall spacers.

7. A method of forming an array of isolation gate constructions in the fabrication of recessed access devices, comprising:

using space between anisotropically etched sidewall spacers in forming mask openings in an etch mask for forming all isolation trenches within the semiconductor material within all of the array;

using the etch mask while etching all of the isolation trenches into the semiconductor material within all of the array through the mask openings; and

forming individual isolation gate constructions in the individual isolation trenches.

8. The method of claim 7 wherein the isolation gate constructions individually comprise an elevationally innermost surface, the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another being within no greater than 40 Angstroms of elevational thickness of the semiconductor material.

9. The method of claim 7 comprising forming individual recessed access gate constructions in individual recessed access device trenches formed in the semiconductor material.

10. A method of forming an array of recessed access device gate constructions and isolation gate constructions, comprising:

using the width of an anisotropically etched sidewall spacer in forming mask openings in an etch mask for forming recessed access device trenches within semiconductor material within the array;

using space between anisotropically etched sidewall spacers in forming second mask openings in the etch mask for forming all isolation trenches within the semiconductor material within all of the array;

using the etch mask while simultaneously etching the recessed access device trenches into the semiconductor material within the array through the first mask openings and all of the isolation trenches into the semiconductor material within all of the array through the second mask openings;

the isolation trenches being formed deeper into the semiconductor material than are the recessed access device trenches; and

forming individual isolation gate constructions in the individual isolation trenches and individual recessed access gate constructions in the individual recessed access device trenches.

11. The method of claim 10 wherein the simultaneously etching forms all of the recessed access device trenches that are within all of the array.

12. A method of forming an array of recessed access device gate constructions and isolation gate constructions, comprising:

forming spaced first features over semiconductor material, the first features comprising spaced first sets of immediately adjacent first features, the immediately adjacent first features within individual first sets being closer to one another than spacing between immediately adjacent first sets;

forming masking material over opposing lateral sidewalls of the first features, the masking material spanning completely between immediately adjacent first features within the first sets, the masking material not spanning completely between immediately adjacent first sets;

removing the first features from between the masking material and forming spaced second features, the second features comprising spaced second sets of immediately adjacent second features, the immediately adjacent second features within individual second sets being closer to one another than spacing between immediately adjacent second sets;

simultaneously etching isolation trenches and recessed access device trenches into the semiconductor material using the second sets as a mask, the recessed access device trenches being formed through mask openings between immediately adjacent second features within the second sets, the isolation trenches being formed through mask openings between the second sets and being formed deeper into the semiconductor material than are the recessed access device trenches; and

forming individual isolation gate constructions in the individual isolation trenches and individual recessed access gate constructions in the individual recessed access device trenches.

13. The method of claim 12 wherein the first features comprise masking blocks and the second features comprise masking blocks, the number of first feature masking blocks in each of the first sets is the same and the number of second feature masking blocks in each of the second sets is the same, the number of second feature masking blocks in the second sets being one greater than the number of first feature masking blocks in the first sets.

14. The method of claim 13 wherein the number of second feature masking blocks in the second sets is 3 and the number of first feature masking blocks in the first set is 2.

15. The method of claim 12 wherein forming the spaced first features comprises:

forming anisotropically etched sidewall spacers over masking blocks received over a hard-mask material;

removing the masking blocks from between the sidewall spacers; and

etching into the hard-mask material using the sidewall spacers as a mask and forming the spaced first features from the hard-mask material.

16. The method of claim 12 wherein forming the spaced second features comprises etching into a hard-mask material underlying the masking material and forming the spaced second features from the hard-mask material.

17. The method of claim 12 wherein,

forming the spaced first features comprises:

forming anisotropically etched sidewall spacers over masking blocks received over a first hard-mask material;

removing the masking blocks from between the sidewall spacers; and

etching into the first hard-mask material using the sidewall spacers as a mask and forming the spaced first features from the first hard-mask material; and

forming the spaced second features comprises;

etching into a second hard-mask material underlying the masking material and forming the spaced second features from the second hard-mask material.

18. A method of forming an array of recessed access device gate constructions and isolation gate constructions, comprising:

forming an initial feature pattern in a first hard-mask, the initial feature pattern comprising blocks for forming recessed access device trenches within semiconductor material within the array;

forming spacer material over sidewalls of the blocks;

removing the blocks from between the spacer material to form a subsequent feature pattern comprising first mask openings for forming the recessed access device trenches within semiconductor material within the array and comprising second mask openings for forming isolation trenches within the semiconductor material within the array;

transferring the subsequent feature pattern to a second hard-mask overlying the semiconductor material;

using the second hard-mask comprising the transferred feature pattern in simultaneously etching the recessed access device trenches and the isolation trenches into the semiconductor material within the array; and

forming individual isolation gate constructions in the individual isolation trenches and individual recessed access gate constructions in the individual recessed access device trenches.

19. The method of claim 18 wherein the simultaneously etching forms all of the recessed access device trenches that are within all of the array.

20. The method of claim 18 wherein the simultaneously etching forms all of the isolation trenches that are within all of the array.

21. The method of claim 18 wherein,

the simultaneously etching forms all of the recessed access device trenches that are within all of the array;

and

the simultaneously etching forms all of the isolation trenches that are within all of the array.

22. The method of claim 18 wherein the isolation trenches are formed deeper into the semiconductor material than are the recessed access device trenches

23. An array of recessed access devices, comprising:

a plurality of isolation gate constructions within isolation trenches formed in semiconductor material;

at least two recessed access device gate constructions individually within individual gate trenches formed in the semiconductor material between immediately adjacent the isolation gate constructions;

source/drain regions between the recessed access device gate constructions and between the isolation gate constructions and the recessed access device gate constructions; and

the recessed access device gate constructions individually comprising a conductive gate having an elevationally outermost conductive surface, the elevationally outermost conductive surfaces of all of the recessed access device gate constructions within all of the array relative one another being within no greater than 50 Angstroms of elevational thickness of the semiconductor material.

24. The array of claim 23 wherein the elevationally outermost conductive surfaces of all of the recessed access device gate constructions within all of the array relative one another are within no greater than 25 Angstroms of elevational thickness of the semiconductor material.

25. The array of claim 24 wherein the elevationally outermost conductive surfaces of all of the recessed access device gate constructions within all of the array relative one another being within no greater than 10 Angstroms of elevational thickness of the semiconductor material.

26. The array of claim 23 wherein the isolation and recessed access device gate constructions individually comprise a first conductive gate material received within and projecting elevationally outward of a second conductive gate material, the first and second conductive gate materials being of different compositions, the elevationally outermost surface being of the first conductive gate material.

27. An array of recessed access devices, comprising:

a plurality of isolation gate constructions within isolation trenches formed in semiconductor material;

at least two recessed access device gate constructions individually within individual gate trenches formed in the semiconductor material between immediately adjacent the isolation gate constructions;

source/drain regions between the recessed access device gate constructions and between the isolation gate constructions and the recessed access device gate constructions; and

the isolation gate constructions individually comprising an elevationally innermost surface, the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another being within no greater than 40 Angstroms of elevational thickness of the semiconductor material.

28. The array of claim 27 wherein the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another are within no greater than 20 Angstroms of elevational thickness of the semiconductor material.

29. The array of claim 28 wherein the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another are within no greater than 10 Angstroms of elevational thickness of the semiconductor material.

30. The array of claim 27 wherein the elevationally innermost surfaces are dielectric.

31. The array of claim 27 wherein the recessed access device gate constructions individually comprise a conductive gate having an elevationally outermost conductive surface, the elevationally outermost conductive surfaces of all of the conductive gates within the array relative one another being within no greater than 50 Angstroms of elevational thickness of the semiconductor material.

32. The array of claim 31 wherein,

the elevationally outermost conductive surfaces of all of the conductive gates within all of the array relative one another being within no greater than 25 Angstroms of elevational thickness of the semiconductor material;

and

the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another being within no greater than 20 Angstroms of elevational thickness of the semiconductor material.

33. The array of claim 32 wherein,

the elevationally outermost conductive surfaces of all of the conductive gates within all of the array relative one another being within no greater than 10 Angstroms of elevational thickness of the semiconductor material;

and

the elevationally innermost surfaces of all of the isolation gate constructions within all of the array relative one another being within no greater than 10 Angstroms of elevational thickness of the semiconductor material.