TRENCH SEMICONDUCTOR POWER DEVICE AND FABRICATION METHOD THEREOF

• US 20130049107A1
• Filed: 06/29/2010
• Published: 02/28/2013
• Est. Priority Date: 02/03/2010
• Status: Abandoned Application

• Current Assignee: M-MOS Semiconductor HK Ltd.
• Original Assignee: M-MOS Semiconductor HK Ltd.
• Inventors: So, Koon Chong
• Application Number:
  US13/576,702
• Publication Number:
  US 20130049107A1
• Time in Patent Office: Days
• US Class Current: 257/331
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench semiconductor power device and a fabrication method. The fabrication method includes: eroding an n epitaxial layer on an n+ substrate to form multiple gate trenches, and implanting with dopants to form source regions and P type base regions, respectively; eroding an interlayer dielectric to form a trench plug; and eroding an aluminum copper alloy to form a metal pad layer and wires. The method forms the source regions and the base regions by directly implanting, does not need source region masks and base region masks, has a simple fabrication process, and improves the quality and reliability of the device.

Claims

1. A method of manufacturing a trench semiconductor power device, comprising the following steps:

1) etching an epitaxial layer on a substrate through a trench mask to form a plurality of gate electrode trenches, and injecting a doping agent to form a source region and a base region respectively;

2) etching an interlayer dielectric through a contact hole mask to form contact trenches, and filling the contact trenches to form trench plugs; and

3) etching metal through a metal mask to form a metal pad layer and wires.

2. The method of manufacturing a trench semiconductor power device according to claim 1, wherein step 1) further comprises the following steps:

1) dry-etching an exposed oxide layer through the trench mask;

2) injecting an N-type doping agent, and diffusing the N-type doping agent into the epitaxial layer by annealing treatment to form the source region;

3) forming trenches in the epitaxial layer, and removing the oxide layer;

4) treating the trenches by sacrificing treatment, and filling the trenches, to form gate electrode trenches;

5) injecting a P-type doping agent to form a base region, and diffusing the base region into the epitaxial layer by annealing treatment.

3. The method of manufacturing a trench semiconductor power device according to claim 1, wherein step 1) further comprises the following steps:

1) dry-etching an exposed oxide layer through the trench mask;

2) forming trenches in the epitaxial layer, and removing the oxide layer;

3) treating the trenches by sacrificing treatment, and filling the trenches, to form gate electrode trenches;

4) injecting a P-type doping agent to form the base region, and diffusing the P-type base region into the epitaxial layer by annealing treatment;

5) injecting an N-type doping agent into the P-type base region to form the source region, and diffusing the N-type source region into the P-type base region by annealing treatment.

4. The method of manufacturing a trench semiconductor power device according to claim 1, wherein step 2) further comprises the following steps:

1) forming an interlayer dielectric on a top layer, and forming the contact trenches through the contact hole mask;

2) filling the contact trenches to form trench plugs.

5. The method of manufacturing a trench semiconductor power device according to claim 1, wherein step 3) comprises depositing a layer of Al—

Cu alloy on the interlayer dielectric, and then etching the metal through the metal mask to form the metal pad layer and wires.

6. The method of manufacturing a trench semiconductor power device according to claim 2, wherein the procedure of treating the trenches by sacrificing treatment and filling the trenches to form gate electrode trenches further comprises the following steps:

1) treating the trenches by sacrificing oxidation;

2) forming a thin gate oxide layer on the exposed side walls and bottom of the trenches and the upper surface of the epitaxial layer by thermal growth; and

3) depositing polysilicon that contains doping agent in the trenches to form a polysilicon layer, filling the trenches and covering a top surface of the trenches, and polishing the polysilicon layer chemically and mechanically.

7. The method of manufacturing a trench semiconductor power device according to claim 2, wherein the injection of N-type doping agent is accomplished by directly injecting an N-type doping agent through the oxide layer into the epitaxial layer, i.e., the procedures of formation of an oxide layer, exposure of the oxide layer through source region mask and etching of the oxide layer before injection of the doping agent through the oxide layer are omitted.

8. The method of manufacturing a trench semiconductor power device according to claim 2, wherein the injection of P-type doping agent is accomplished by directly injecting a P-type doping agent through the thin gate oxide layer into the epitaxial layer, i.e., the procedures of formation of an oxide layer and exposure of the oxide layer through base region mask and etching of the oxide layer before injection of the doping agent through the thin gate oxide layer are omitted.

9. The method of manufacturing a trench semiconductor power device according to claim 3, wherein the injection of N-type doping agent is accomplished by directly injecting an N-type doping agent through the thin gate oxide layer into the P-type base region, i.e., the procedures of formation of an oxide layer and exposure of the oxide layer through source region mask and etching of the oxide layer before injection of the doping agent through the thin gate oxide layer are omitted.

10. The method of manufacturing a trench semiconductor power device according to claim 4, wherein step 1) further comprises the following steps:

1) depositing B-P glass and non-doped silicon dioxide on the top layer to form the interlayer dielectric;

2) etching the interlayer dielectric through contact hole mask, to form contact trenches;

3) etching the N-type source region, so that the contact trenches penetrate through the source region into the base region wherein the source region comprises an N-type source region, and the base region comprises a P-type base region; and

4) Filling the contact trenches to form trench plugs.

11. The method of manufacturing a trench semiconductor power device according to claim 10, wherein, in step 3), the etching of the N-type source region comprises etching the entire N-type source region and partial gate electrode trenches in a terminal region.

12. The method of manufacturing a trench semiconductor power device according to claim 4, wherein step 2) further comprises the following steps:

dry-etching the contact trenches and depositing a titanium/titanium nitride layer on side walls and a bottom of the contact trenches, and then filling the contact trenches with tungsten to form the trench plugs, and etching a surface layer of the contact trenches to remove the titanium/titanium nitride and tungsten on a top layer of the interlayer dielectric.

13. A semiconductor power device, manufactured with the manufacturing method as described in claim 1, wherein, the manufacturing method further comprises:

depositing a metal layer on a bottom of the substrate.

14. A semiconductor power device, comprising an N-channel trench power MOSFET manufactured with the manufacturing method as described in claim 1.

15. A semiconductor power device, comprising a P-channel trench power MOSFET manufactured with the manufacturing method as described in claim 1.

16. The method of manufacturing a trench semiconductor power device according to claim 3, wherein the procedure of treating the trenches by sacrificing treatment and filling the trenches to form gate electrode trenches further comprises the following steps:

1) treating the trenches by sacrificing oxidation;

2) forming a thin gate oxide layer on the exposed side walls and bottom of the trenches and the upper surface of the epitaxial layer by thermal growth; and

3) depositing polysilicon that contains doping agent in the trenches to form a polysilicon layer, filling the trenches and covering a top surface of the trenches, and polishing the polysilicon layer chemically and mechanically.

17. The method of manufacturing a trench semiconductor power device according to claim 3, wherein the injection of P-type doping agent is accomplished by directly injecting a P-type doping agent through the thin gate oxide layer into the epitaxial layer, i.e., the procedures of formation of an oxide layer and exposure of the oxide layer through base region mask and etching of the oxide layer before injection of the doping agent through the thin gate oxide layer are omitted.