SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device, comprising:
- a first chip mounting portion;
a first conductor portion;
a first semiconductor chip having a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; and
a sealing portion sealing therein the first semiconductor chip, and at least a part of each of the first chip mounting portion and the first conductor portion,wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other,wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, while the second MOSFET is an element for detecting a current flowing in the first MOSFET and formed in a second region of the first main surface of the first semiconductor chip,wherein the second region has an area smaller than that of the first region,wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, first and second source pads electrically coupled to a source of the first MOSFET, and a third source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip,wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip,wherein the first source pad of the first semiconductor chip is electrically coupled to the first conductor portion via a first conductor plate,wherein the first source pad is a pad for outputting a current flowing in the first MOSFET, while the second source pad is a pad for sensing a source voltage of the first MOSFET,wherein the first source pad is formed of a first source wire formed in the first region, while the second source pad is formed of a second source wire,wherein the second source wire has one end thereof coupled to the first source wire, andwherein, in planar view, the second source pad is at a position not overlapping the first conductor plate, and a coupled portion between the second source wire and the first source wire is at a position overlapping the first conductor plate.
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Accused Products
Abstract
A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.
78 Citations
21 Claims
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1. A semiconductor device, comprising:
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a first chip mounting portion; a first conductor portion; a first semiconductor chip having a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; and a sealing portion sealing therein the first semiconductor chip, and at least a part of each of the first chip mounting portion and the first conductor portion, wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other, wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, while the second MOSFET is an element for detecting a current flowing in the first MOSFET and formed in a second region of the first main surface of the first semiconductor chip, wherein the second region has an area smaller than that of the first region, wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, first and second source pads electrically coupled to a source of the first MOSFET, and a third source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip, wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip, wherein the first source pad of the first semiconductor chip is electrically coupled to the first conductor portion via a first conductor plate, wherein the first source pad is a pad for outputting a current flowing in the first MOSFET, while the second source pad is a pad for sensing a source voltage of the first MOSFET, wherein the first source pad is formed of a first source wire formed in the first region, while the second source pad is formed of a second source wire, wherein the second source wire has one end thereof coupled to the first source wire, and wherein, in planar view, the second source pad is at a position not overlapping the first conductor plate, and a coupled portion between the second source wire and the first source wire is at a position overlapping the first conductor plate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A semiconductor device, comprising:
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a first chip mounting portion; a second chip mounting portion; a first conductor portion; a first semiconductor chip including a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; a second semiconductor chip having a second main surface, and a second back surface opposite to the second main surface and bonded to the second chip mounting portion; and a sealing portion sealing therein the first semiconductor chip, the second semiconductor chip, and at least a part of each of the first chip mounting portion, the second chip mounting portion, and the first conductor portion, wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other, wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, wherein the second MOSFET is an element for detecting a current flowing in the first MOSFET, and is formed in a second region of the first main surface of the first semiconductor chip, wherein the second region has an area smaller than that of the first region, wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, first and second source pads electrically coupled to a source of the first MOSFET, and a third source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip, wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip, wherein the first source pad is for outputting the current flowing in the first MOSFET, wherein the second semiconductor chip is formed with a control circuit for controlling the first and second MOSFETs, wherein first, second, third, and fourth pads are formed over the second main surface of the second semiconductor chip, and wherein the first source pad of the first semiconductor chip is electrically coupled to the first conductor portion via a first conductor plate, the first pad of the second semiconductor chip is electrically coupled to the first gate pad via a first wire, the second pad of the second semiconductor chip is electrically coupled to the first conductor plate via a second wire, the third pad of the second semiconductor chip is electrically coupled to the third source pad via a third wire, and the fourth pad of the second semiconductor chip is electrically coupled to the second source pad via a fourth wire. - View Dependent Claims (15, 16, 17, 18)
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19. A semiconductor device, comprising:
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a first chip mounting portion; a second chip mounting portion; a third chip mounting portion; a first semiconductor chip including a first main surface, and a first back surface opposite to the first main surface and bonded to the first chip mounting portion; a second semiconductor chip having a second main surface, and a second back surface opposite to the second main surface and bonded to the second chip mounting portion; a third semiconductor chip having a third main surface, and a third back surface opposite to the third main surface and bonded to the third chip mounting portion; and a sealing portion sealing therein the first semiconductor chip, the second semiconductor chip, the third semiconductor chip, and at least a part of each of the first chip mounting portion, the second chip mounting portion, and the third chip mounting portion, wherein the first semiconductor chip is formed with a first MOSFET and a second MOSFET which have respective drains thereof electrically coupled to each other, and respective gates thereof electrically coupled to each other, wherein the first MOSFET is formed in a first region of the first main surface of the first semiconductor chip, while the second MOSFET is an element for detecting a current flowing in the first MOSFET and formed in a second region of the first main surface of the first semiconductor chip, wherein the second region has an area smaller than that of the first region, wherein a first gate pad electrically coupled to the gates of the first and second MOSFETs, first and second source pads electrically coupled to a source of the first MOSFET, and a third source pad electrically coupled to a source of the second MOSFET are formed over the first main surface of the first semiconductor chip, wherein a drain electrode electrically coupled to the drains of the first and second MOSFETs is formed over the first back surface of the first semiconductor chip, wherein the third semiconductor chip is formed with a third MOSFET, wherein a second gate pad electrically coupled to a gate of the third MOSFET and a fifth source pad electrically coupled to a source of the third MOSFET are formed over the third main surface of the third semiconductor chip, wherein a drain electrode electrically coupled to a drain of the third MOSFET is formed over the third back surface of the third semiconductor chip, wherein the second semiconductor chip is formed with a control circuit for controlling the first and second MOSFETs, wherein first, second, third, fourth, and fifth pads are formed over the second main surface of the second semiconductor chip, and wherein the first source pad of the first semiconductor chip is electrically coupled to the third chip mounting portion via a first conductor plate, the first pad of the second semiconductor chip is electrically coupled to the first gate pad via a first wire, the second pad of the second semiconductor chip is electrically coupled to the third chip mounting portion via a second wire, the third pad of the second semiconductor chip is electrically coupled to the third source pad via a third wire, and the fourth pad of the second semiconductor chip is electrically coupled to the second source pad via a fourth wire. - View Dependent Claims (20, 21)
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Specification