RESISTOR AND MANUFACTURING METHOD THEREOF

• US 20130049168A1
• Filed: 08/23/2011
• Published: 02/28/2013
• Est. Priority Date: 08/23/2011
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Yang, Jie-Ning, Wang, Yao-Chang, Yeh, Chiu-Hsien, Hsu, Shih-Chieh, Pai, Chi-Horn, Tseng, Chi-Sheng, Tseng, Kun-Szu, Chou, Ying-Hung
• Granted Patent: US 8,981,527 B2
• Time in Patent Office: Days
• US Class Current: 257/538
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/20 Resistors

Abstract

A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.

Claims

1. A method for forming a resistor integrated with a transistor having metal gate, comprising:

providing a substrate having a transistor region and a resistor region defined thereon;

forming a transistor in the transistor region and a polysilicon main portion in the resistor region, the transistor having a polysilicon dummy gate and the polysilicon main portion with two doped regions positioned at two opposite ends;

performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches; and

forming a metal gate in the first trench and metal structures respectively in the second trenches.

2. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, wherein the substrate further comprises a polysilicon layer blanketly formed thereon.

3. The method for forming a resistor integrated with a transistor having metal gate according to claim 2, further comprising performing an ion implantation to form the two doped regions in the polysilicon layer in the resistor region.

4. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, further comprising forming a patterned hard mask exposing the polysilicon dummy gate and a portion of the doped regions on the substrate before the etching process.

5. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, wherein the substrate further comprises a high dielectric constant (high-k) layer and a bottom barrier layer sequentially formed thereon.

6. The method for forming a resistor integrated with a transistor having metal gate according to claim 5, wherein the high-k dielectric layer and the bottom barrier layer are formed between the substrate and the polysilicon layer.

7. The method for forming a resistor integrated with a transistor having metal gate according to claim 6, wherein the bottom barrier layer is exposed in the first trench and the second trenches by the etching process.

8. The method for forming a resistor integrated with a transistor having metal gate according to claim 5, wherein the high-k dielectric layer and the bottom barrier layer are sequentially formed in the first trench and the second trenches after the etching process.

9. The method for forming a resistor integrated with a transistor having metal gate according to claim 8, wherein a topmost portion of the high-k dielectric layer and the bottom barrier layer is lower than an opening of the second trenches.

10. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, wherein the doped region comprises an L shape after the etching process.

11. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, wherein a width of the doped region is larger than a width of the second trench.

12. The method for forming a resistor integrated with a transistor having metal gate according to claim 1, further comprising forming a first contact electrically connected to the metal gate and second contacts electrically connected to the metal structures respectively.

13. A resistor comprising:

a substrate;

a polysilicon main portion formed on the substrate;

two metal portions respectively positioned at two opposite ends of the polysilicon main portion on the substrate; and

two doped regions respectively formed between the metal portions and the polysilicon main portion on the substrate.

14. The resistor according to 13, further comprising a high-k dielectric layer and a bottom barrier layer sequentially formed on the substrate.

15. The resistor according to claim 14, wherein the high-k dielectric layer and the bottom barrier layer are formed between the substrate and the polysilicon main portion, between the substrate and the metal portion, and between the substrate and the doped region.

16. The resistor according to claim 14, wherein the high-k dielectric layer and the bottom barrier layer are sandwiched by the metal portion and the doped region.

17. The resistor according to claim 16, wherein the doped region is an L-shaped region.

18. The resistor according to claim 13, wherein topmost portions of the high-k dielectric layer and the bottom barrier layer are lower than a surface of the metal portion.

19. The resistor according to claim 13, wherein a width of the doped region is defined depending on a required resistance.

20. The resistor according to claim 13 further comprising contacts electrically connecting to the metal portions, respectively.