DRIVE CIRCUIT, DISPLAY, AND METHOD OF DRIVING DISPLAY

• US 20130050304A1
• Filed: 08/06/2012
• Published: 02/28/2013
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yoshinaga, Tomoro
• Granted Patent: US 8,963,967 B2
• Time in Patent Office: Days
• US Class Current: 345/694
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2320/0209 Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
• CPC Class Codes: G09G 2320/0266 Reduction of sub-frame artefacts
• CPC Class Codes: G09G 3/2033 with splitting one or more sub-frames corresponding to the most significant bits into two or more sub-frames
• CPC Class Codes: G09G 3/36 using liquid crystals

Abstract

A drive circuit includes: a division section that divides one frame period into a subfields, and divides each of one or more of the subfields to generate division subfields; a correction section that corrects, when bit arrays of the gray-scale data corresponding to respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and an ON-OFF-period control section that controls a ratio of an ON period or an OFF period to the one frame period, by turning on or off a liquid crystal cell of each of pixels according to the bit corresponding to each of the subfields and each of the division subfields.

Claims

1. A drive circuit driving each of pixels that are arranged in matrix in a display, each of the pixels being provided with a built-in memory that includes a liquid crystal cell, the drive circuit comprising:

a division section dividing one frame period into a plurality of subfields, and dividing each of one or more of the plurality of subfields to generate a plurality of division subfields, each of the plurality of subfields corresponding to each bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and each of the one or more of the plurality of subfields having the period that is relatively long and being divided into periods each equal to the period of the subfield that is relatively short;

a correction section correcting, when bit arrays of the gray-scale data corresponding to the respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and

an ON-OFF-period control section controlling a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.

2. The drive circuit according to claim 1, wherein, when the bit arrays of the respective two pixels are still different even after the bit array of the gray-scale data corresponding to the first pixel is brought closer to the bit array of the gray-scale data corresponding to the second pixel while the gray-scale is maintained, the correction section corrects one of the gray-scale data of the respective two pixels that has the higher gray-scale to be increased.

3. The drive circuit according to claim 1, wherein the correction section adds a correction value common to all the pixels to the gray-scale data corresponding to each of all the pixels and periodically changes the correction value for every frame.

4. A display with a display region and a drive circuit, the display region being provided with pixels that are arranged in matrix and each having a built-in memory that includes a liquid crystal cell, and the drive circuit driving each of the pixels, the drive circuit comprising:

a division section dividing one frame period into a plurality of subfields, and dividing each of one or more of the plurality of subfields to generate a plurality of division subfields, each of the plurality of subfields corresponding to each bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and each of the one or more of the plurality of subfields having the period that is relatively long and being divided into periods each equal to the period of the subfield that is relatively short;

a correction section correcting, when bit arrays of the gray-scale data corresponding to the respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and

an ON-OFF-period control section controlling a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.

5. A method of driving a display, the display being provided with pixels that are arranged in matrix and each having a built-in memory that includes a liquid crystal cell, the method comprising:

dividing one frame period into a plurality of subfields, and dividing each of one or more of the plurality of subfields to generate a plurality of division subfields, each of the plurality of subfields corresponding to each bit of gray-scale data and having a period corresponding to a weight of the corresponding bit, and each of the one or more of the plurality of subfields having the period that is relatively long and being divided into periods each equal to the period of the subfield that is relatively short;

correcting, when bit arrays of the gray-scale data corresponding to the respective two pixels next to each other are different from one another, the bit array of the gray-scale data corresponding to a first pixel of the two pixels to bring this bit array closer to the bit array of the gray-scale data corresponding to a second pixel of the two pixels, while maintaining gray-scale; and

controlling a ratio of an ON period or an OFF period to the one frame period, by turning on or off the liquid crystal cell of each of the pixels according to the bit corresponding to each of the subfields and each of the division subfields.