Delay Restricted Channel Estimation for Multi-Carrier Systems

• US 20130051450A1
• Filed: 10/01/2012
• Published: 02/28/2013
• Est. Priority Date: 01/28/2005
• Status: Active Grant

• Current Assignee: AT&T Intellectual Property I LP (AT&T, Inc.)
• Original Assignee: AT&T Intellectual Property I LP (AT&T, Inc.)
• Inventors: Ghosh, Arunabha
• Granted Patent: US 8,649,254 B2
• Time in Patent Office: Days
• US Class Current: 375/232
• CPC Class Codes: H04L 25/0216 with estimation of channel length
• CPC Class Codes: H04L 25/022 of frequency response
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

A method includes multiplying, at a device, a suppressed estimate of a channel by a first matrix to obtain a delay restricted estimate of the channel. The method also includes demodulating a signal received via the channel based at least in part on the delay restricted estimate of the channel.

Claims

1. A method comprising:

multiplying, at a device, a suppressed estimate of a channel by a first matrix to obtain a delay restricted estimate of the channel; and

demodulating a signal received via the channel based at least in part on the delay restricted estimate of the channel.

2. The method of claim 1, wherein the first matrix is a unitary matrix.

3. The method of claim 1, further comprising suppressing some but not all elements of a second matrix representing an estimate of the channel to obtain the suppressed estimate of the channel.

4. The method of claim 3, further comprising performing a channel estimation to obtain the estimate of the channel based on the received signal, wherein the channel estimation comprises a zero-forcing channel estimation.

5. The method of claim 4, further comprising determining a set of symbols of the received signal based on the delay restricted estimate of the channel.

6. The method of claim 5, wherein determining the set of symbols comprises dividing each received symbol of the received signal by a particular element of the delay restricted estimate of the channel.

7. The method of claim 4, further comprising estimating a noise variance from a noise estimate obtained by subtracting an estimated signal from the received signal.

8. The method of claim 7, wherein the estimated signal is determined by multiplying a preamble symbol matrix by the delay restricted estimate of the channel.

9. The method of claim 3, wherein the second matrix is obtained from an operation on a third matrix and wherein the third matrix is a transform matrix to transform a set of symbols from a first domain representation to a second domain representation.

10. The method of claim 9, wherein the transform matrix is a Fourier transform matrix.

11. The method of claim 9, wherein the operation includes a singular value decomposition.

12. The method of claim 3, wherein suppression of an element of the second matrix comprises setting the element to zero.

13. The method of claim 3, wherein the elements to be suppressed are determined based on a channel impulse response associated with the received signal and a number of sub-carriers associated with the received signal.

14. An apparatus, comprising:

a multiplier configured to multiply a suppressed channel estimate by a first matrix to obtain a delay restricted estimate of the channel; and

a demodulator configured to demodulate a signal received via the channel based at least in part on the delay restricted estimate of the channel.

15. The apparatus of claim 14, further comprising a suppressor configured to suppress some but not all elements of a second matrix representing a channel estimate to obtain the suppressed channel estimate of the channel, wherein a particular element of the second matrix is suppressed by setting the particular element to zero and wherein the first matrix is unitary and is obtained from a singular value decomposition of a Fourier transform matrix.

16. The apparatus of claim 14, further comprising:

a channel estimator configured to compute the channel estimate based on the received signal; and

an equalizer configured to equalize the received signal based on the delay restricted estimate.

17. The apparatus of claim 16, wherein the channel estimator is further configured compute the channel estimate based on a pilot symbol diagonal matrix, a vector of received symbols, the first matrix, or any combination thereof.

18. A computer-readable device, comprising instructions that, when executed by a processor, cause the processor to:

multiply a suppressed estimate of a channel by a first matrix to obtain a delay restricted estimate of the channel; and

demodulate a signal received via the channel based at least in part on the delay restricted estimate of the channel.

19. The computer-readable device of claim 18, further comprising instructions that, when executed by the processor, cause the processor to suppress some but not all elements of a second matrix representing an estimate of the channel to obtain the suppressed estimate of the channel, wherein suppression of an element of the second matrix comprises setting the element to zero and wherein the first matrix is a unitary matrix obtained from a singular value decomposition of a Fourier transform matrix.

20. The computer-readable device of claim 19, further comprising instructions that, when executed by the processor, cause the processor to perform a channel estimation to obtain the estimate of the channel based on the received signal, wherein the channel estimate is obtained further based on an inverse of a pilot symbol diagonal matrix, a vector of received symbols, and a conjugate transpose of the first matrix.