System and Method for Low Distortion Capacitive Signal Source Amplifier

• US 20130051582A1
• Filed: 08/25/2011
• Published: 02/28/2013
• Est. Priority Date: 08/25/2011
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kropfitsch, Michael, Ceballos, Jose Luis
• Granted Patent: US 9,236,837 B2
• Time in Patent Office: Days
• US Class Current: 381/111
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/03 the amplifier being designed for audio applications
• CPC Class Codes: H03F 2200/105 A non-specified detector of the power of a signal being used in an amplifying circuit
• CPC Class Codes: H03F 2200/165 A filter circuit coupled to the input of an amplifier
• CPC Class Codes: H03F 2200/211 the input of an amplifier can be attenuated by a continuously controlled transistor attenuator
• CPC Class Codes: H03F 2200/213 A variable capacitor being added in the input circuit, e.g. base, gate, of an amplifier stage
• CPC Class Codes: H03F 3/183 with semiconductor devices only
• CPC Class Codes: H03F 3/187 in integrated circuits
• CPC Class Codes: H04R 19/005 using semiconductor materials
• CPC Class Codes: H04R 19/04 Microphones H04R19/01 takes precedence
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.

Claims

1. A method comprising:

amplifying a signal provided by a capacitive signal source to form an amplified signal;

detecting a peak voltage of the amplified signal; and

adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage, the controllable impedance being adjusted to a value inversely proportional to the detected peak voltage.

2. The method of claim 1, further comprising:

comparing the detected peak voltage to a predetermined threshold; and

adjusting the controllable impedance comprises

decreasing the controllable impedance if the detected peak voltage exceeds the predetermined threshold,

increasing the controllable impedance if detected peak voltage does not exceed the predetermined threshold.

3. The method of claim 2, wherein

decreasing the controllable impedance comprises decreasing the controllable impedance at a first rate;

and

increasing the controllable impedance comprises increasing the controllable impedance at a second rate.

4. The method of claim 3, wherein the first rate is greater than the second rate.

5. The method of claim 1, wherein increasing the controllable impedance comprises increasing the controllable impedance up to a maximum value in a plurality of steps.

6. The method of claim 1, wherein adjusting the controllable impedance comprises adjusting a capacitance coupled to the output of the capacitive signal source.

7. The method of claim 6, wherein the adjusting the capacitance comprises adjusting a capacitance of a capacitor array, adjusting the capacitance of the capacitor array coupling and decoupling capacitors to and from the output of the capacitive signal source.

8. The method of claim 1, wherein adjusting the controllable impedance comprises adjusting a controllable resistance coupled to the output of the capacitive signal source.

9. The method of claim 1, further comprising:

detecting a zero crossing of the signal provided by the capacitive signal source; and

adjusting the controllable impedance comprises adjusting the controllable impedance when a zero crossing is detected.

10. The method of claim 1, wherein:

the capacitive signal source comprises a MEMS microphone; and

the adjustable impedance is controlled such that a total harmonic distortion of the amplified signal is less than 10% for a 140 dBSPL acoustic input to the MEMS microphone.

11. The method of claim 1, wherein:

the capacitive signal source comprises a MEMS microphone; and

the method further comprises biasing the MEMS microphone.

12. A method comprising:

amplifying a signal provided by a capacitive signal source to form an amplified signal;

detecting a peak voltage of the amplified signal; and

adjusting a controllable bias voltage of the capacitive signal source in response to detecting the peak voltage, bias voltage of the capacitive signal source being adjusted to a value inversely proportional to the detected peak voltage.

13. The method of claim 12, wherein:

the capacitive signal source comprises a MEMS microphone; and

the controllable bias is controlled such that a total harmonic distortion of the amplified signal is less than 10% for a 140 dBSPL acoustic input to the MEMS microphone.

14. A system for amplifying a signal provided by a capacitive signal source, the system comprising:

a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;

a controllable attenuation circuit coupled to the input node of the signal amplifier, the controllable attenuation circuit configured to provide a controllable input impedance at the input node of the signal amplifier;

a signal detection circuit coupled to an output of the signal amplifier, the signal detection circuit configured to detect peak signal values at the output of the signal amplifier; and

a control circuit coupled between the signal detection circuit and the controllable attenuation circuit, the control circuit configured to adjust the controllable attenuation circuit in response to changes in detected peak signal values.

15. The system of claim 14, wherein the signal detection circuit is configured to detect a positive peak signal value and a negative peak signal value.

16. The system of claim 14, wherein:

the signal detection circuit is further configured to detect a zero crossing of a signal at the output of the signal amplifier; and

the control circuit is further configured to adjust the controllable attenuation circuit when the signal detection circuit detects a zero crossing.

17. The system of claim 14, wherein the control circuit is further configured to command the controllable attenuation circuit to decrease the input impedance if the signal detection circuit detects a peak signal level greater than a threshold and increase the input impedance up to a maximum value in several steps if the signal detection circuit does not detect a peak signal level greater than the threshold.

18. The system of claim 17, wherein the control circuit commands the controllable attenuation circuit to decrease the input impedance at a first rate and increase the input impedance at a second rate.

19. The system of claim 18, wherein the first rate is greater than the second rate.

20. The system of claim 14, wherein the controllable attenuation circuit comprises a selectable capacitor array coupled to the input node of the signal amplifier.

21. The system of claim 14, wherein the controllable attenuation circuit comprises an adjustable resistance coupled to the input node of the signal amplifier.

22. The system of claim 14, wherein the capacitive signal source comprises a MEMS microphone.

23. A system for amplifying a signal provided by a capacitive signal source, the system comprising:

a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;

a controllable bias circuit configured to be coupled to a bias node of the capacitive signal source, the controllable bias circuit configured to provide a controllable bias voltage to the capacitive signal source;

a signal detection circuit coupled to an output of the signal amplifier, the signal detection circuit configured to detect peak signal values at the output of the signal amplifier; and

a control circuit coupled between the signal detection circuit and the controllable bias circuit, the control circuit configured to adjust the controllable bias circuit in response to changes in detected peak signal values.

24. The system of claim 23, wherein the control circuit is further configured to command the controllable bias circuit to decrease controllable bias voltage if the signal detection circuit detects a peak signal level greater than a threshold and increase the controllable bias voltage if the signal detection circuit does not detect a peak signal level greater than the threshold.

25. The system of claim 24, wherein the control circuit commands the controllable bias circuit to decrease the controllable bias voltage at a first rate and increase the controllable bias voltage at a second rate, wherein the first rate is greater than the second rate.

26. The system of claim 23, wherein the controllable bias circuit comprises:

a digital-to-analog converter (DAC) coupled to an output of the control circuit; and

a charge pump circuit coupled to an output of the DAC;

a lowpass filter coupled between the charge pump circuit and an output of the controllable bias circuit.

27. The system of claim 27, wherein the capacitive signal source comprises a MEMS microphone.

28. An integrated circuit for amplifying a signal provided by a capacitive signal source, the integrated circuit comprising:

a signal amplifier comprising an input node configured to be coupled to the capacitive signal source;

a controllable attenuation circuit coupled to the input node of the signal amplifier;

a peak detector coupled to an output of the signal amplifier;

a comparator coupled to an output of the peak detector and the output of the signal amplifier, the comparator configured to compare an output of the peak detector with a threshold; and

a control circuit coupled between the an output of the comparator and a control input of the controllable attenuation circuit.

29. The integrated circuit of claim 28, wherein the control circuit comprises:

a counter coupled to the output of the comparator, the counter being configured to increment if the output of the peak detector exceeds the threshold and decrement if the output of the peak detector does not exceed the threshold; and

a look-up table circuit coupled to the output of the counter.

30. The integrated circuit of claim 28, wherein:

the integrated circuit further comprises a single-ended to differential conversion circuit coupled between the signal amplifier and the peak detector;

the peak detector comprises a positive peak detector and a negative peak detector; and

the comparator comprises a differential comparator configured to compare an output of the positive peak detector with a positive threshold, and an output of the negative peak detector with a negative threshold.

31. The integrated circuit of claim 28, further comprising a zero crossing detector coupled to the output of the signal amplifier, wherein the control circuit is configured to adjust the controllable attenuation circuit when the zero crossing detector detects a zero crossing.

32. The integrated circuit of claim 28, wherein the controllable attenuation circuit comprises:

a plurality of capacitors; and

a plurality of switches coupled between the plurality of capacitors and the input of the signal amplifier, the plurality of switches being controllable by the control circuit.

33. The integrated circuit of claim 28, wherein the controllable attenuation circuit comprises a controllable resistor.

34. The integrated circuit of claim 33, wherein the controllable resistor comprises:

a first transistor coupled between the input of the signal amplifier and a reference voltage;

a second transistor having a drain coupled to a gate of the first transistor;

a plurality of switchable resistors coupled between a gate of the second transistor and the drain of the second transistor, the plurality of switchable resistors controllable by the control circuit; and

a current source coupled to the gate of the second transistor.