MEMORY REFRESH METHODS AND APPARATUSES

• US 20130055046A1
• Filed: 08/31/2011
• Published: 02/28/2013
• Est. Priority Date: 08/31/2011
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Blodgett, Greg A.
• Granted Patent: US 9,176,800 B2
• Time in Patent Office: Days
• US Class Current: 714/764
• CPC Class Codes: G06F 11/0727 in a storage system, e.g. in a DASD or network based storage system drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/076 by exceeding a count or rate limit, e.g. word- or bit count limit
• CPC Class Codes: G06F 11/0793 Remedial or corrective actions recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data

Abstract

Apparatuses and memory refresh methods are disclosed, such as those involving checking a portion of a memory device for errors in response to the memory device being powered on, and reprogramming corrected data to the memory device if errors are found in checking the portion of the nonvolatile memory for errors. Other apparatuses and memory refresh methods are disclosed.

Claims

1. A method, comprising:

checking a portion of memory of a memory device for errors in response to the memory device being powered on; and

reprogramming corrected data to the memory if errors are found.

2. The method of claim 1, wherein the portion of the memory checked for errors comprises a block or less of the memory.

3. The method of claim 1, wherein checking a portion of memory for errors comprises determining whether the portion of the memory is already marked for refresh upon powering on the memory device.

4. The method of claim 3, further comprising refreshing the portion of the memory if it is determined that the portion is already marked.

5. The method of claim 1, wherein checking a portion of memory for errors comprises reading the portion of the memory and using an error correction code to determine the presence of errors.

6. The method of claim 1, wherein reprogramming corrected data to the memory if errors are found comprises reprogramming corrected data only if the errors found exceed an error threshold.

7. The method of claim 1, further comprising checking additional portions of the memory for errors during operation of the memory.

8. The method of claim 7, wherein checking additional portions of the memory for errors during operation is triggered by a number of memory pages read.

9. The method of claim 1, further comprising maintaining a refresh block pointer identifying a memory block to be checked for read errors.

10. The method of claim 1, wherein reprogramming corrected data to the memory comprises marking the portion of the memory for refresh, copying data of the portion of the memory, reprogramming the copied data, and unmarking the portion of the memory.

11. An apparatus, comprising:

an array of memory cells; and

a controller operable to check a portion of the memory cells for errors in response to at least a portion of the apparatus being powered on, and reprogram corrected data to the memory cells if errors are found.

12. The apparatus of claim 11, wherein the array of nonvolatile memory comprises a NAND flash memory.

13. The apparatus of claim 11, wherein the controller is further operable to determine whether a portion of the memory is marked for refresh in response to the at least a portion of the apparatus being powered on, and to refresh the portion of memory if the controller determines that the portion is marked for refresh.

14. The apparatus of claim 11, wherein the controller being operable to check a portion of the memory cells for errors comprises the controller being operable to use error correction code data associated with the user data read from the portion of the memory cells to determine whether errors are present in the read user data.

15. The apparatus of claim 11, wherein the controller being operable to reprogram corrected data comprises the controller being operable to reprogram data corrected data to the memory cells if the errors found exceed an error threshold.

16. The apparatus of claim 11, wherein the controller is further operable to check additional portions of the memory cells for errors during operation of the memory cells.

17. The apparatus of claim 16, wherein the controller being operable to check additional portions of the memory cells for errors during operation comprises the controller being operable to check additional portions of the memory cells for errors responsive to a number of pages being read during operation.

18. The apparatus of claim 11, further comprising a stored refresh block pointer identifying a block of the memory not yet checked for errors.

19. The apparatus of claim 11, wherein the controller being operable to reprogram the portion of nonvolatile memory comprises the controller being further operable to store a marker indicating the portion of the memory for refresh, copy the portion of memory, reprogram the data to the memory, and remove the stored marker indicating the portion of memory when reprogramming is complete.

20. The apparatus of claim 11, wherein the array of memory cells comprises an array of multi-level memory cells.

21. A controller operable to check a portion of a memory for errors in response to the controller being powered on, and to refresh the portion of the memory in response to errors found in checking the portion for errors.

22. The controller of claim 21, wherein the controller is further operable to determine whether a portion of the memory is marked for refresh in response to being powered on, and to refresh a portion of the memory if it is marked.

23. The controller of claim 21, wherein the controller is further operable to apply an error correction code to the read portion of nonvolatile memory to detect presence of the errors and to remove the errors from the portion of nonvolatile memory.

24. The controller of claim 21, wherein the controller is further operable to mark the portion of nonvolatile memory for refresh, copy the portion of nonvolatile memory, correct the errors found in the portion of memory, reprogram corrected data to the memory, and unmark the portion of memory.

25. The controller of claim 21, wherein the controller is further operable to check the memory for errors as a background method while the memory is available for normal access operations.

26. The controller of claim 25, wherein the controller is operable to check the nonvolatile memory device for errors as a background process based on a number of memory pages read.

27. The controller of claim 21, wherein the controller is operable to refresh the portion of the nonvolatile memory only if found errors exceed an error threshold.

28. An apparatus, comprising:

a controller operable to check a portion of a memory for errors in response to at least a portion of the apparatus being powered on, and refresh the portion of the memory in response to errors found in checking the portion of the memory for errors.

29. The apparatus of claim 28, further comprising a memory device including the memory.

30. The apparatus of claim 29, wherein the memory device comprises a flash memory card.

31. The apparatus of claim 28, wherein the controller is further operable to determine whether a portion of the memory is marked for refresh and to refresh the marked portion of the memory in response to the at least a portion of the apparatus being powered on.

32. The apparatus of claim 28, wherein the controller is further operable to check additional portions of the memory for errors and to refresh portions with errors while the memory is available for normal operations.

33. The apparatus of claim 32, wherein the controller is further operable to check additional portions of the memory for errors based on a number of memory pages read.

34. The apparatus of claim 28, wherein the controller is further operable to mark the portion of the memory as needing to be refreshed, copy data of the portion of memory, and correct any correctable errors in the portion of memory, reprogram the corrected data to the memory, and unmark the portion of memory as needing to be refreshed.

35. The apparatus of claim 28, wherein the apparatus comprises a portable gaming device, a smart phone, a digital camera, a personal digital assistant, a solid state flash drive, or a computer.

36. A method, comprising:

checking a portion of memory of a memory device for errors in response to the memory device being powered on; and

when errors are found, refreshing the portion of memory.

37. The method of claim 36, wherein checking a portion of the memory for errors comprises checking a marker identifying a portion of the memory that needs to be refreshed in response to powering on the memory device.

38. The method of claim 36, further comprising checking additional portions of the memory for errors during normal operation of the memory device.

39. The method of claim 36, further comprising storing a refresh block pointer identifying a memory block to be checked for read errors in the memory device, and storing a refresh page pointer identifying a memory page to be checked for read errors in the memory block.

40. A method comprising:

responsive to powering on a memory device, reading data of an identified block of memory of the memory device;

determining whether the read data of the identified block of memory includes a number of errors exceeding a threshold; and

if the number of errors exceeds the threshold, marking the identified block for refresh.

41. The method of claim 40, further comprising, prior to reading data of the identified block, determining whether a block of memory of the memory device is already marked for refresh and, if a block is already marked for refresh, refreshing the already marked block.

42. The method of claim 41, wherein the data of the identified block is only read if no block is already marked for refresh.

43. The method of claim 41, wherein reading the data of the identified block is further responsive to refreshing the already marked block.

44. The method of claim 41, wherein determining whether a block of memory is already marked for refresh comprises checking a location in nonvolatile memory.

45. The method of claim 41, wherein determining whether a block of memory is already marked for refresh comprises checking a flag associated with the block of memory.

46. The method of claim 40, further comprising refreshing the identified block responsive to marking the identified block for refresh.

47. The method of claim 46, wherein refreshing the identified block comprises copying the data of the identified block and reprogramming the data of the identified block.

48. The method of claim 40, wherein determining whether the read data of the identified block of memory includes a number of errors exceeding a threshold comprises counting a number of errors per page of data read from the identified block.

49. The method of claim 40, wherein reading data of an identified block of memory of the memory device comprises looking up a pointer to a pre-identified block responsive to powering on the memory device and then reading data of the identified block.

50. The method of claim 49, further comprising changing a block identified by the pointer responsive to refreshing the identified block.

51. The method of claim 40, wherein reading data of an identified block of memory of the memory device comprises reading data of a single identified block of memory.

52. The method of claim 40, wherein determining whether the read data of the identified block of memory includes a number of errors exceeding a threshold comprises determining whether a number of errors in any page of data read from the identified block exceeds the threshold.

53. The method of claim 46, wherein refreshing the identified block comprises:

copying the data of the identified block;

correcting correctable errors in the copied data; and

reprogramming the corrected data.

54. A method comprising:

determining whether a number of memory page reads exceeds a threshold;

if the number of memory page reads exceeds the threshold, reading data stored in a particular number of memory pages of a block of memory; and

if a number of errors in the read data exceeds a threshold, marking the block of memory for refresh.

55. The method of claim 54, wherein determining whether a number of memory page reads exceeds a threshold comprises:

incrementing an up-counter responsive to reading a page of memory; and

determining whether a value of the incremented up-counter exceeds a particular value.

56. The method of claim 54, wherein determining whether a number of memory page reads exceeds a threshold comprises:

decrementing a down-counter responsive to reading a page of memory; and

determining whether a value of the decremented down-counter is below a particular value.

57. The method of claim 54, wherein reading data stored in a particular number of memory pages of a block of memory comprises reading data stored in a particular number of memory pages of an identified block of memory.

58. The method of claim 57, wherein reading data stored in a particular number of memory pages of an identified block of memory comprises reading data stored in a particular number of memory pages of a single identified block of memory.

59. The method of claim 57, wherein reading data stored in a particular number of memory pages of an identified block of memory comprises reading data stored in a particular number of memory pages of a block of memory identified by a refresh block pointer.

60. The method of claim 54, wherein marking the block of memory for refresh comprises marking the block of memory for refresh if a number of errors in any page of the read data exceeds a threshold.