BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM

• US 20130055048A1
• Filed: 08/09/2012
• Published: 02/28/2013
• Est. Priority Date: 08/22/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: PARK, CHUL-WOO, HWANG, HONG-SUN, SON, JONG-PIL, YU, HAK-SOO, KANG, UK-SONG, CHOI, JOO-SUN
• Granted Patent: US 8,769,356 B2
• Time in Patent Office: Days
• US Class Current: 714/773
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/24 Accessing extra cells, e.g. dummy cells or redundant cells
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

Claims

1. A memory device, comprising:

a memory cell array comprising a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells; and

a bad page map that stores bad page location information indicating whether each of the pages of the first memory block is good or bad,

wherein a fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

2. The memory device of claim 1, wherein the bad page map indicates the bad page location information using an anti-fuse circuit.

3. The memory device of claim 1, wherein fail page addresses of the first memory block are replaced by pass page addresses of the second memory block in a reverse direction starting from a maximum page address of the second memory block.

4. The memory device of claim 1, further comprising:

a first page control unit that generates a first access page address to block an address to the fail page address of the first memory block; and

a second page control unit that generates a second access page address to allow access to the pass page address of the second memory block.

5. The memory device of claim 4, wherein the first page control unit comprises:

a first storage unit that stores a memory access page address received from an external source;

a second storage unit that stores the fail page address of the first memory block;

a comparator that compares the memory access page address of the first storage unit with the fail page address of the second storage unit; and

a logic circuit unit that receives the memory access page address of the first storage unit and an output of the comparator and outputs the first access page address.

6. The memory device of claim 4, wherein the second page control unit comprises:

a first storage unit that stores a memory access page address received from an external source;

a second storage unit that stores the pass page address of the second memory block that replaces the fail page address of the first memory block;

a selection control unit that stores a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block; and

a selection unit that selects the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputs a result of the selection as the second access page address.

7. The memory device of claim 1, wherein the memory device does not comprise a redundancy memory cell array that replaces bad cells generated in the memory cell array.

8. A memory system, comprising:

a memory device comprising a first memory block, a second memory block, and a bad page map that stores bad page location information of the first memory block; and

a memory controller that stores fail page addresses of the first memory block and pass page addresses of the second memory block that respectively replace the fail page addresses, according to bit information transmitted by the bad page map.

9. The memory system of claim 8, wherein the memory device stores bad page location information indicating whether each of the pages of the first memory block is good or bad.

10. The memory system of claim 9, wherein the memory device stores the bad page location information in the form of a bit.

11. The memory system of claim 9, wherein the memory device sequentially transmits units of bit information indicating whether each of the pages of the first memory block is good or bad to the memory controller, starting from a least significant page address of the first memory block.

12. The memory system of claim 11, wherein the memory controller comprises:

a counter that generates a page address sequentially increased from the least significant page address of the first memory block; and

a sorting unit that stores the page address of the counter as the fail page address according to the bit information of the bad page map.

13. The memory system of claim 8, wherein the memory controller stores the pass page addresses of the second memory block in a reverse direction starting from a maximum page address of the second memory block.

14. The memory system of claim 8, wherein the memory controller further comprises:

a first storage unit that stores the fail page addresses; and

a second storage unit that stores the pass page addresses,

wherein the memory controller compares a requested page address received from a host with the fail page addresses and outputs the requested page address or the pass page address as an access page address of the memory device according to a comparison result.

15. The memory system of claim 14, wherein the first storage unit is a content addressable memory (CAM) type storage unit.

16. The memory system of claim 14, wherein the second storage unit is a static random-access memory (SRAM) type storage unit.

17. A method of operating a memory device comprising a memory cell array and a bad page map, comprising:

storing, in the bad page map, bad page location information indicating whether each page in a first memory block of the memory cell array is good or bad; and

replacing a fail page address of the first memory block with a pass page address in a second memory block of the memory cell array according to the bad page location information.

18. The method of claim 17, wherein the bad page location information comprises a bit.

19. The method of claim 17, wherein storing the bad page location information comprises changing a state of an anti-fuse circuit.

20. The method of claim 17, further comprising replacing fail page addresses of the first memory block by pass page addresses of the second memory block in a reverse direction starting from a maximum page address of the second memory block.