×

BAD PAGE MANAGEMENT IN MEMORY DEVICE OR SYSTEM

  • US 20130055048A1
  • Filed: 08/09/2012
  • Published: 02/28/2013
  • Est. Priority Date: 08/22/2011
  • Status: Active Grant
First Claim
Patent Images

1. A memory device, comprising:

  • a memory cell array comprising a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells; and

    a bad page map that stores bad page location information indicating whether each of the pages of the first memory block is good or bad,wherein a fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×