SYSTEMATIC, NORMALIZED METRIC FOR ANALYZING AND COMPARING OPTIMIZATION TECHNIQUES FOR INTEGRATED CIRCUITS EMPLOYING VOLTAGE SCALING AND INTEGRATED CIRCUITS DESIGNED THEREBY

• US 20130055175A1
• Filed: 08/30/2012
• Published: 02/28/2013
• Est. Priority Date: 05/07/2008
• Status: Abandoned Application

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Inventors: Jamann, Joseph J., Parker, James C., Rao, Vishwas M.
• Application Number:
  US13/599,549
• Publication Number:
  US 20130055175A1
• Time in Patent Office: Days
• US Class Current: 716/103
• CPC Class Codes: G01R 31/31725 Timing aspects, e.g. clock distribution, skew, propagation delay for tester hardware G01R31/31937
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/215 using field-effect transistors

Abstract

Various embodiments of methods of designing an integrated circuit (IC) are provided herein. One embodiment of one such method includes: (1) generating a functional IC design, (2) determining a target clock rate for the functional IC design, (3) generating a netlist from the functional IC design that meets the target clock rate, (4) determining a unitless performance/power quantifier from the netlist, (5) attempting to increase the unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in the netlist, wherein the attempting is performed by a processor and (6) generating a layout of the IC from the netlist.

Claims

1. A method of designing an integrated circuit, comprising:

generating a functional integrated circuit design;

determining a target clock rate for said functional integrated circuit design;

generating a netlist from said functional integrated circuit design that meets said target clock rate;

determining a unitless performance/power quantifier from said netlist;

attempting to increase said unitless performance/power quantifier by changing at least one of a speed, an area and a power consumption in at least some noncritical paths in said netlist, wherein said attempting is performed by a processor; and

generating a layout of said integrated circuit from said netlist.

2. The method as recited in claim 1 further comprising determining a target area for said functional integrated circuit design.

3. The method as recited in claim 1 further comprising determining a target power consumption for said functional integrated circuit design.

4. The method as recited in claim 1 further comprising determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling.

5. The method as recited in claim 1 wherein said attempting comprises attempting to increase said unitless performance/power quantifier by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist.

6. The method as recited in claim 1 wherein said attempting comprises attempting to increase said unitless performance/power quantifier by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist.

7. The method as recited in claim 1 wherein said attempting is carried out only with respect to true noncritical paths in said netlist.

8. An integrated circuit designed by the method as recited in claim 1.

9. A method of designing an integrated circuit, comprising:

generating a functional integrated circuit design;

determining a target clock rate for said functional integrated circuit design;

determining a target area for said functional integrated circuit design;

determining a target power consumption for said functional integrated circuit design;

determining whether said integrated circuit is to employ voltage scaling or adaptive voltage scaling;

generating a netlist from said functional integrated circuit design that meets said target clock rate;

determining a unitless performance/power quantifier from said netlist;

attempting to increase said unitless performance/power quantifier by changing all of said speed, said area and said power consumption in said at least some noncritical paths in said netlist, wherein said attempting is performed by a processor; and

generating a layout of said integrated circuit from said netlist.

10. The method as recited in claim 9 wherein said attempting comprises attempting to increase said unitless performance/power quantifier by changing said at least one of said speed, said area and said power consumption in all of said noncritical paths in said netlist.

11. The method as recited in claim 9 wherein said attempting is carried out only with respect to true noncritical paths in said netlist.

12. An integrated circuit designed by the method as recited in claim 9.

13. A method of designing an integrated circuit, comprising:

calculating a unitless performance/power quantifier for said integrated circuit, wherein the calculating is performed by a processor; and

employing said unitless performance/power quantifier to characterize said integrated circuit relative to other integrated circuits.

14. The method as recited in claim 13 wherein said unitless performance/power quantifier is unitless.

15. The method as recited in claim 13 wherein said calculating comprises calculating: