THIN FILM TRANSISTOR SUBSTRATE, LCD DEVICE INCLUDING THE SAME, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE

• US 20130056729A1
• Filed: 05/16/2011
• Published: 03/07/2013
• Est. Priority Date: 06/08/2010
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Misaki, Katsunori
• Granted Patent: US 8,507,916 B2
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: G02F 1/13629 Multilayer wirings
• CPC Class Codes: G02F 1/136295 Materials; Compositions; Manufacture processes
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A source electrode and a drain electrode are formed by a stack of a titanium layer, a molybdenum nitride layer, an aluminum layer, and a molybdenum nitride layer, the titanium layer is formed by dry etching, and an oxide semiconductor layer is formed by performing annealing in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

Claims

1. A thin film transistor substrate, comprising:

a base substrate; and

a thin film transistor having a gate electrode provided on the base substrate, a gate insulating film provided so as to cover the gate electrode, a semiconductor layer comprised of an oxide semiconductor and provided on the gate insulating film so as to overlap the gate electrode, and a source electrode and a drain electrode which are provided on the gate insulating film so as to face each other on the semiconductor layer and so that a part of the source electrode and a part of the drain electrode are connected to the semiconductor layer, wherein

the source electrode and the drain electrode have a stack of a first conductive layer, a second conductive layer, and a third conductive layer,

the third conductive layer is comprised of a low resistance metal that causes a redox reaction with the oxide semiconductor,

the first conductive layer directly contacts the semiconductor layer, is formed by dry etching, and is comprised of a refractory metal including a Group 4 metal element that is less likely to cause the redox reaction with the oxide semiconductor than the third conductive layer does, an alloy primarily containing the Group 4 metal element, or a nitride or oxide thereof,

the second conductive layer is comprised of a refractory metal including a Group 5 or Group 6 metal element into which metal particles of the third conductive layer are less likely to diffuse than into the first conductive layer, an alloy primarily containing the Group 5 or Group 6 metal element, or a nitride or oxide thereof, and

the semiconductor layer is formed by performing annealing in an oxygen-containing atmosphere after formation of the source electrode and the drain electrode.

2. The thin film transistor substrate of claim 1, wherein

the first conductive layer contains titanium,

the second conductive layer contains at least one element selected from molybdenum, chromium, niobium, tantalum, and tungsten, and

the third conductive layer contains at least one element selected from aluminum, copper, and silver.

3. The thin film transistor substrate of claim 1, wherein

the thin film transistor is covered by a protective insulating film comprised of silicon oxide.

4. The thin film transistor substrate of claim 1, wherein

the gate insulating film is comprised of silicon oxide.

5. The thin film transistor substrate of claim 1, further comprising:

a pixel electrode provided for each thin film transistor, and connected to the drain electrode of the thin film transistor,

the source electrode and the drain electrode further have a fourth conductive layer on the third conductive layer, and

the fourth conductive layer of the drain electrode is directly connected to the pixel electrode, and a difference in ionization tendency between the fourth conductive layer and the pixel electrode and between the fourth conductive layer and the third conductive layer is smaller than that between the pixel electrode and the third conductive layer.

6. The thin film transistor substrate of claim 1, wherein

the first conductive layer has a thickness in a range of 5 nm to 50 nm, both inclusive.

7. The thin film transistor substrate of claim 1, wherein

the semiconductor layer is comprised of an indium gallium zinc oxide-based oxide semiconductor.

8. A liquid crystal display device, comprising:

the thin film transistor substrate of claim 1;

a counter substrate placed so as to face the thin film transistor substrate; and

a liquid crystal layer provided between the thin film transistor substrate and the counter substrate.

9. A method for manufacturing the thin film transistor substrate of claim 1, comprising:

a first patterning step of forming the gate electrode by forming a conductive film on the base substrate and patterning the conductive film by using a first photomask;

a gate insulating film formation step of forming the gate insulating film so as to cover the gate electrode;

a second patterning step of forming the semiconductor layer by forming on the gate insulating film a semiconductor film comprised of an oxide semiconductor, and patterning the semiconductor film by using a second photomask; and

a third patterning step of forming the source electrode and the drain electrode by sequentially forming a first conductive film, a second conductive film, and a third conductive film to form a stacked conductive film so as to cover the semiconductor layer, patterning the second and third conductive films of the stacked conductive film by wet etching using a third photomask, and then patterning the remaining first conductive film by dry etching, wherein

the first conductive film is comprised of a refractory metal including a Group 4 metal element, an alloy primarily containing the Group 4 metal element, or a nitride or oxide thereof, the second conductive layer is comprised of a refractory metal including a Group 5 or Group 6 metal element, an alloy primarily containing the Group 5 or Group 6 metal element, or a nitride or oxide thereof, and the third conductive layer is comprised of a low resistance metal that causes a redox reaction with the oxide semiconductor, and

the substrate having both the source electrode and the drain electrode formed thereon is subjected to annealing in an oxygen-containing atmosphere.

10. The method of claim 9, further comprising:

a fourth patterning step of forming a contact hole at a position corresponding to the drain electrode by forming a protective insulating film so as to cover the source electrode and the drain electrode and patterning the protective insulating film by using a fourth photomask; and

a fifth patterning step of forming a pixel electrode so as to connect to the drain electrode, by forming on the protective insulating film a conductive film so as to connect to the drain electrode via the contact hole, and patterning the conductive film by using a fifth photomask.

11. The method of claim 10, wherein

the annealing is performed after formation of the protective insulating film in the fourth patterning step.

12. The method of claim 9, wherein

the oxide semiconductor is indium gallium zinc oxide-based oxide semiconductor.