SEMICONDUCTOR WAFER, METHOD OF PRODUCING SEMICONDUCTOR WAFER, ELECTRONIC DEVICE, AND METHOD OF PRODUCING ELECTRONIC DEVICE

• US 20130056794A1
• Filed: 10/30/2012
• Published: 03/07/2013
• Est. Priority Date: 04/30/2010
• Status: Active Grant

• Current Assignee: Sumitomo Chemical Company Limited
• Original Assignee: Sumitomo Chemical Company Limited
• Inventors: NISHIKAWA, Naohiro, NAKANO, Tsuyoshi, INOUE, Takayuki
• Granted Patent: US 9,559,196 B2
• Time in Patent Office: Days
• US Class Current: 257/190
• CPC Class Codes: H01L 21/02463 Arsenides
• CPC Class Codes: H01L 21/02505 consisting of more than two layers
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 27/085 including field-effect components only
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7785 with more than one donor layer
• CPC Class Codes: H01L 29/812 with a Schottky gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence; with Schottky contact on top of heterojunction gate H01L29/802

Abstract

A semiconductor wafer includes a base wafer, a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type, a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion, and a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.

Claims

1. A semiconductor wafer comprising:

a base wafer;

a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type;

a separation layer that is formed over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion; and

a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.

2. The semiconductor wafer as set forth in claim 1, wherein

the separation layer contains impurity atoms the number of which is sufficient to allow the separation layer to trap all of the majority carriers of the first conductivity type in the first semiconductor portion.

3. The semiconductor wafer as set forth in claim 2, wherein

the base wafer is made of GaAs, and

the separation layer is made of Al_yGa_1-yAs (0≦

y≦

1) doped with an oxygen atom.

4. The semiconductor wafer as set forth in claim 3, wherein

the first channel layer and the second channel layer are made of In_zGa_1-zAs (0≦

z≦

1).

5. The semiconductor wafer as set forth in claim 1, wherein

the impurity concentration of the separation layer is less than 1×

10²¹ (cm<sup>−

3</sup>).

6. The semiconductor wafer as set forth in claim 1, wherein

the separation layer has an electron trap center to trap electrons, the center being lower than the boundary of the conduction band of the separation layer by 0.25 eV or more.

7. The semiconductor wafer as set forth in claim 1, wherein

the separation layer has a hole trap center to trap holes, the center being higher than the boundary of the valence band of the separation layer by 0.25 eV or more.

8. The semiconductor wafer as set forth in claim 1, wherein

the separation layer contains an oxygen atom, a boron atom, a chromium atom or an iron atom.

9. The semiconductor wafer as set forth in claim 1, wherein

the first channel layer contains electron carriers the number of which is larger than the total of the number of electron carriers contained in the second channel layer and the number of electron carriers contained in the separation layer, and

the second channel layer contains hole carriers the number of which is larger than the total of the number of hole carriers contained in the first channel layer and the number of hole carriers contained in the separation layer.

10. The semiconductor wafer as set forth in claim 1, further comprising

an etching stop layer that is formed between the separation layer and the first semiconductor portion and is configured such that the etching rate of the etching stop layer under a prescribed etching condition is lower than the etching rate of the separation layer.

11. The semiconductor wafer as set forth in claim 10, wherein

the etching stop layer lattice-matches or pseudo lattice-matches the first semiconductor portion and the separation layer, and the separation layer lattice-matches or pseudo lattice-matches the second semiconductor portion.

12. The semiconductor wafer as set forth in claim 10, wherein

the etching stop layer is made of i-In_tGa_1-tP (0≦

t≦

1).

13. The semiconductor wafer as set forth in claim 1, wherein

the first semiconductor portion further includes a first carrier supply layer containing an n-type impurity to supply the first channel layer with an electron,

the second semiconductor portion further includes a second carrier supply layer containing a p-type impurity to supply the second channel layer with a hole, and

the separation layer contains carriers the number of which is larger than one of the number of n-type carriers in the first carrier supply layer and the number of p-type carriers in the second carrier supply layer.

17. A method of producing an electronic device, comprising:

forming a mask to cover a partial region of the semiconductor wafer as set forth in claim 1;

removing the second semiconductor portion by etching in a region other than a mask region in which the mask has been formed;

forming a mask removed region by removing the mask, after the removal of the second semiconductor portion by the etching;

forming a source electrode, a gate electrode and a drain electrode in the first semiconductor portion in the region other than the mask region; and

forming a source electrode, a gate electrode and a drain electrode in the second semiconductor portion in the mask removed region.

14. A method of producing a semiconductor wafer, comprising;

forming, on a base wafer, a first semiconductor portion including a first channel layer containing a majority carrier of a first conductivity type;

forming, over the first semiconductor portion, a separation layer containing an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion; and

forming, over the separation layer, a second semiconductor portion including a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type.

15. The method as set forth in claim 14 of producing a semiconductor wafer, further comprising

forming, over the first semiconductor portion, an etching stop layer that is configured such that the etching rate of the etching stop layer under a prescribed etching condition is lower than the etching rate of the separation layer.

16. An electronic device comprising:

a base wafer;

a first semiconductor portion that is formed on the base wafer and includes a first channel layer containing a majority carrier of a first conductivity type;

a separation layer that is formed in a partial region over the first semiconductor portion and contains an impurity to create an impurity level deeper than the impurity level of the first semiconductor portion;

a second semiconductor portion that is formed over the separation layer and includes a second channel layer containing a majority carrier of a second conductivity type opposite to the first conductivity type;

a source electrode, a gate electrode and a drain electrode formed in the first semiconductor portion; and

a source electrode, a gate electrode and a drain electrode formed in the second semiconductor portion.